MC908QY8CDWE Datasheet, PDF (123/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

ESCI During Break Interrupts
13.5.2 Stop Mode
The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states.
ESCI module operation resumes after the MCU exits stop mode.
Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission
or reception results in invalid data.
13.6 ESCI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared.After the break, doing the
second step clears the status bit.
13.7 I/O Signals
The ESCI module can share its pins with the general-purpose I/O pins. See Figure 13-1 for the port pins
that are shared.
13.7.1 ESCI Transmit Data (TxD)
The TxD pin is the serial data output from the ESCI transmitter. When the ESCI is enabled, the TxD pin
becomes an output.
13.7.2 ESCI Receive Data (RxD)
The RxD pin is the serial data input to the ESCI receiver. When the ESCI is enabled, the RxD pin becomes
an input.
13.8 Registers
The following registers control and monitor operation of the ESCI:
• ESCI control register 1, SCC1
• ESCI control register 2, SCC2
• ESCI control register 3, SCC3
• ESCI status register 1, SCS1
• ESCI status register 2, SCS2
• ESCI data register, SCDR
• ESCI baud rate register, SCBR
• ESCI prescaler register, SCPSC
• ESCI arbiter control register, SCIACTL
• ESCI arbiter data register, SCIADAT
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor
121