MC908QY8CDWE Datasheet, PDF (128/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Enhanced Serial Communications Interface (ESCI) Module
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables ESCI error interrupt requests generated by the receiver overrun bit, OR.
1 = ESCI error interrupt requests from OR bit enabled
0 = ESCI error interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables ESCI error interrupt requests generated by the noise error bit, NE.
1 = ESCI error interrupt requests from NE bit enabled
0 = ESCI error interrupt requests from NE bit disabled
FEIE — Receiver Framing Error Interrupt Enable Bit
This read/write bit enables ESCI error interrupt requests generated by the framing error bit, FE.
1 = ESCI error interrupt requests from FE bit enabled
0 = ESCI error interrupt requests from FE bit disabled
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables ESCI receiver interrupt requests generated by the parity error bit, PE.
1 = ESCI error interrupt requests from PE bit enabled
0 = ESCI error interrupt requests from PE bit disabled
13.8.4 ESCI Status Register 1
ESCI status register 1 (SCS1) contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Bit 7
6
5
4
3
2
1
Bit 0
Read: SCTE
TC
SCRF
IDLE
OR
NF
FE
PE
Write:
Reset: 1
1
0
0
0
0
0
0
= Unimplemented
Figure 13-12. ESCI Status Register 1 (SCS1)
SCTE — ESCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register.
SCTE can generate an ESCI transmitter interrupt request. When the SCTIE bit in SCC2 is set, SCTE
generates an ESCI transmitter interrupt request. In normal operation, clear the SCTE bit by reading
SCS1 with SCTE set and then writing to SCDR
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
MC68HC908QB8 Data Sheet, Rev. 3
126
Freescale Semiconductor