MC908QY8CDWE Datasheet, PDF (163/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Functional Description
remain low between transmissions. This format may be preferable in systems having only one master and
only one slave driving the MISO data line.
SPSCK CYCLE #
FOR REFERENCE
SPSCK; CPOL = 0
1
2
3
4
5
6
7
8
SPSCK; CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
SS; TO SLAVE
CAPTURE STROBE
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
LSB
Figure 15-6. Transmission Format (CPHA = 1)
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This
causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. After the
transmission begins, no new data is allowed into the shift register from the transmit data register.
Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of
SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the
shift register after the current transmission.
15.3.3.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA
has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle.
When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and
the start of the SPI transmission. (See Figure 15-7.) The internal SPI clock in the master is a free-running
derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and
SPMSTR bits are set. Because the SPI clock is free-running, it is uncertain where the write to the SPDR
occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown
in Figure 15-7. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU
bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus
cycles for DIV128.
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor
161