MC908QY8CDWE Datasheet, PDF (51/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Registers
3.8.4 ADC10 Clock Register (ADCLK)
This register selects the clock frequency for the ADC10 and the modes of operation.
Read:
Write:
Reset:
Bit 7
ADLPC
0
6
5
4
3
2
1
ADIV1 ADIV0 ADICLK MODE1 MODE0 ADLSMP
0
0
0
0
0
0
Figure 3-7. ADC10 Clock Register (ADCLK)
Bit 0
ACLKEN
0
ADLPC — ADC10 Low-Power Configuration Bit
ADLPC controls the speed and power configuration of the successive approximation converter. This
is used to optimize power consumption when higher sample rates are not required.
1 = Low-power configuration: The power is reduced at the expense of maximum clock speed.
0 = High-speed configuration
ADIV[1:0] — ADC10 Clock Divider Bits
ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK.
Table 3-3 shows the available clock configurations.
Table 3-3. ADC10 Clock Divide Ratio
ADIV1
0
0
1
1
ADIV0
0
1
0
1
Divide Ratio (ADIV)
1
2
4
8
Clock Rate
Input clock ÷ 1
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
ADICLK — Input Clock Select Bit
If ACLKEN is clear, ADICLK selects either the bus clock or an alternate clock source as the input clock
source to generate the internal clock ADCK. If the alternate clock source is less than the minimum
clock speed, use the internally-generated bus clock as the clock source. As long as the internal clock
ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (f_ADCK) between
the minimum and maximum clock speeds (considering ALPC), correct operation can be guaranteed.
1 = The internal bus clock is selected as the input clock source
0 = The alternate clock source IS SELECTED
MODE[1:0] — 10- or 8-Bit or Hardware Triggered Mode Selection
These bits select 10- or 8-bit operation. The successive approximation converter generates a result
that is rounded to 8- or 10-bit value based on the mode selection. This rounding process sets the
transfer function to transition at the midpoint between the ideal code voltages, causing a quantization
error of ± 1/2LSB.
Reset returns 8-bit mode.
00 = 8-bit, right-justified, ADSCR software triggered mode enabled
01 = 10-bit, right-justified, ADSCR software triggered mode enabled
10 = Reserved
11 = 10-bit, right-justified, hardware triggered mode enabled
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor
49