MC908QY8CDWE Datasheet, PDF (144/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

System Integration Module (SIM)
14.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the
CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when
describing activity on the RST pin.
NOTE
For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles.
The internal reset signal then follows the sequence from the falling edge of
RST shown in Figure 14-4.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see Figure 14-4). An internal reset can be caused by an illegal address, illegal opcode, COP time out,
LVI, or POR (see Figure 14-5).
IRST
RST
BUSCLKX4
ADDRESS
BUS
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 14-4. Internal Reset Timing
VECTOR HIGH
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
Figure 14-5. Sources of Internal Reset
Table 14-2. Reset Recovery Timing
Reset Recovery Type
POR/LVI
All others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
MC68HC908QB8 Data Sheet, Rev. 3
142
Freescale Semiconductor