MC908QY8CDWE Datasheet, PDF (49/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Registers
(with ACLKEN low), continuous conversions will cease and can be restarted only with a write to
ADSCR. Any write to ADSCR with ADCO set and the ADCH bits not all 1s will abort the current
conversion and begin continuous conversions.
If the bus frequency is less than the ADCK frequency, precise sample time for continuous conversions
cannot be guaranteed in short-sample mode (ADLSMP = 0). If the bus frequency is less than 1/11th
of the ADCK frequency, precise sample time for continuous conversions cannot be guaranteed in
long-sample mode (ADLSMP = 1).
When clear, the ADC10 will perform a single conversion (single conversion mode) each time ADSCR
is written (assuming the ADCH[4:0] bits do not decode all 1s).
1 = Continuous conversion following a write to ADSCR
0 = One conversion following a write to ADSCR
ADCH[4:0] — Channel Select Bits
The ADCH[4:0] bits form a 5-bit field that is used to select one of the input channels. The input
channels are detailed in Table 3-2. The successive approximation converter subsystem is turned off
when the channel select bits are all set to 1. This feature allows explicit disabling of the ADC10 and
isolation of the input channel from the I/O pad. Terminating continuous conversion mode this way will
prevent an additional, single conversion from being performed. It is not necessary to set the channel
select bits to all 1s to place the ADC10 in a low-power state, however, because the module is
automatically placed in a low-power state when a conversion completes.
Table 3-2. Input Channel Select
ADCH4
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
ADCH3 ADCH2 ADCH1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
Continuing through
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
ADCH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input Select⁽¹⁾
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Unused
Unused
Unused
AD8
AD9
BANDGAP REF⁽²⁾
Reserved
Reserved
V_REFH
V_REFL
Low-power state
1. If any unused or reserved channels are selected, the resulting conversion will
be unknown.
2. Requires LVI to be powered (LVIPWRD =0, in CONFIG1)
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor
47