MC908QY8CDWE Datasheet, PDF (146/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

System Integration Module (SIM)
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an
illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal
reset sources.
14.4.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the
CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively
pulls down the RST pin for all internal reset sources. See Figure 2-1. Memory Map for memory ranges.
14.4.2.5 Low-Voltage Inhibit (LVI) Reset
The LVI asserts its output to the SIM when the V_DD voltage falls to the LVI trip voltage V_TRIPF. The LVI
bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the
SIM counter counts out 4096 BUSCLKX4 cycles after V_DD rises above V_TRIPR. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
The SIM actively pulls down the (RST) pin for all internal reset sources.
14.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the
oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for
counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of BUSCLKX4.
14.5.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit
asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock
state machine.
14.5.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After
an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the
normal delay of 4096 BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications
using canned oscillators that do not require long start-up times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC cleared in the configuration
register 1 (CONFIG1).
14.5.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see 14.7.2 Stop Mode for details.) The SIM counter is
free-running after all reset states. See 14.4.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.
MC68HC908QB8 Data Sheet, Rev. 3
144
Freescale Semiconductor