MC908QY8CDWE Datasheet, PDF (120/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Enhanced Serial Communications Interface (ESCI) Module
Slow Data Tolerance
Figure 13-7 shows how much a slow received character can be misaligned without causing a noise error
or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
MSB
RECEIVER
RT CLOCK
STOP
DATA SAMPLES
Figure 13-7. Slow Data
For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles
+ 10 RT cycles = 154 RT cycles.
With the misaligned character shown in Figure 13-7, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is 9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is:
-1---5---4-----^–----1----4---7-- ^{× 100 = 4.54%}
154
For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles
+ 10 RT cycles = 170 RT cycles.
With the misaligned character shown in Figure 13-7, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is:
-1---7---0-----^–----1----6---3-- ^{× 100 = 4.12%}
170
Fast Data Tolerance
Figure 13-8 shows how much a fast received character can be misaligned without causing a noise error
or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.
RECEIVER
RT CLOCK
STOP
IDLE OR NEXT CHARACTER
DATA
SAMPLES
Figure 13-8. Fast Data
MC68HC908QB8 Data Sheet, Rev. 3
118
Freescale Semiconductor