MC908QY8CDWE Datasheet, PDF (124/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Enhanced Serial Communications Interface (ESCI) Module
13.8.1 ESCI Control Register 1
ESCI control register 1 (SCC1):
• Enables loop mode operation
• Enables the ESCI
• Controls output polarity
• Controls character length
• Controls ESCI wakeup method
• Controls idle character detection
• Enables parity function
• Controls parity type
Bit 7
6
5
4
3
2
1
Bit 0
Read:
LOOPS ENSCI TXINV
M
WAKE
ILTY
PEN
PTY
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 13-9. ESCI Control Register 1 (SCC1)
LOOPS — Loop Mode Select Bit
This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the
ESCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode.
1 = Loop mode enabled
0 = Normal operation enabled
ENSCI — Enable ESCI Bit
This read/write bit enables the ESCI and the ESCI baud rate generator. Clearing ENSCI sets the SCTE
and TC bits in ESCI status register 1 and disables transmitter interrupts.
1 = ESCI enabled
0 = ESCI disabled
TXINV — Transmit Inversion Bit
This read/write bit reverses the polarity of transmitted data.
1 = Transmitter output inverted
0 = Transmitter output not inverted
NOTE
Setting the TXINV bit inverts all transmitted values including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
This read/write bit determines whether ESCI characters are eight or nine bits long (see
Table 13-4).The ninth bit can serve as a receiver wakeup signal or as a parity bit.
1 = 9-bit ESCI characters
0 = 8-bit ESCI characters
MC68HC908QB8 Data Sheet, Rev. 3
122
Freescale Semiconductor