MC908QY8CDWE Datasheet, PDF (188/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

Timer Interface Module (TIM)
16.8.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH0F
Write: 0
CH0IE
MS0B
MS0A
ELS0B ELS0A
TOV0 CH0MAX
Reset: 0
0
0
0
0
0
0
0
Figure 16-9. TIM Channel 0 Status and Control Register (TSC0)
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH1F
0
CH1IE
MS1A ELS1B ELS1A TOV1 CH1MAX
Write: 0
Reset: 0
0
0
0
0
0
0
0
Figure 16-10. TIM Channel 1 Status and Control Register (TSC1)
Bit 7
6
5
4
3
2
1
Bit 0
Read: CH2F
Write: 0
CH2IE
MS2B
MS2A
ELS2B ELS2A
TOV2 CH2MAX
Reset: 0
0
0
0
0
0
0
0
Figure 16-11. TIM Channel 2 Status and Control Register (TSC2)
Read:
Write:
Reset:
Bit 7
CH3F
0
0
6
5
0
CH3IE
0
0
= Unimplemented
4
MS3A
0
3
ELS3B
0
2
ELS3A
0
1
TOV3
0
Bit 0
CH3MAX
0
Figure 16-12. TIM Channel 3 Status and Control Register (TSC3)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
counter registers matches the value in the TIM channel x registers.
Clear CHxF by reading the TSCx register with CHxF set and then writing a 0 to CHxF. If another
interrupt request occurs before the clearing sequence is complete, then writing 0 to CHxF has no
effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF.
MC68HC908QB8 Data Sheet, Rev. 3
186
Freescale Semiconductor