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MC908QY8CDWE Datasheet, PDF (224/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3
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Electrical Specifications
18.15 3.0-Volt SPI Characteristics
Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Operating frequency
Master
Slave
Cycle time
1
Master
Slave
2
Enable lead time
3
Enable lag time
Clock (SPSCK) high time
4
Master
Slave
Clock (SPSCK) low time
5
Master
Slave
Data setup time (inputs)
6
Master
Slave
Data hold time (inputs)
7
Master
Slave
Access time, slave(3)
8
CPHA = 0
CPHA = 1
9
Disable time, slave(4)
Data valid time, after enable edge
10
Master
Slave(5)
Data hold time, outputs, after enable edge
11
Master
Slave
fOP(M)
fOP(S)
tcyc(M)
tcyc(S)
tLead(S)
tLag(S)
tSCKH(M)
tSCKH(S)
tSCKL(M)
tSCKL(S)
tSU(M)
tSU(S)
tH(M)
tH(S)
tA(CP0)
tA(CP1)
tDIS(S)
tV(M)
tV(S)
tHO(M)
tHO(S)
fOP/128
DC
2
1
1
1
tcyc –35
1/2 tcyc –35
tcyc –35
1/2 tcyc –35
40
40
40
40
0
0
—
—
—
0
0
fOP/2
fOP
128
—
—
—
64 tcyc
—
64 tcyc
—
—
—
—
—
50
50
50
60
60
—
—
1. Numbers refer to dimensions in Figure 18-11 and Figure 18-12.
2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins.
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
Unit
MHz
MHz
tcyc
tcyc
tcyc
tcyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MC68HC908QB8 Data Sheet, Rev. 3
222
Freescale Semiconductor
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