MC908QY8CDWE Datasheet, PDF (195/232 Pages) Freescale Semiconductor, Inc – Addendum to MC68HC908QB8, rev. 3

ADDRESS BUS[15:8]
Break Module (BRK)
ADDRESS BUS[15:0]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
CONTROL
BKPT
(TO SIM)
ADDRESS BUS[7:0]
Figure 17-2. Break Module Block Diagram
The break interrupt timing is:
• When a break address is placed at the address of the instruction opcode, the instruction is not
executed until after completion of the break interrupt routine.
• When a break address is placed at an address of an instruction operand, the instruction is executed
before the break interrupt.
• When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction
is executed.
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can
be generated continuously.
CAUTION
A break address should be placed at the address of the instruction opcode.
When software does not change the break address and clears the BRKA
bit in the first break interrupt routine, the next break interrupt will not be
generated after exiting the interrupt routine even when the internal address
bus matches the value written in the break address registers.
17.2.1.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See 14.8.2 Break Flag Control Register and the Break Interrupts subsection
for each module.
17.2.1.2 TIM During Break Interrupts
A break interrupt stops the timer counter.
17.2.1.3 COP During Break Interrupts
The COP is disabled during a break interrupt in monitor mode when the BDCOP bit is set in the break
auxiliary register (BRKAR).
MC68HC908QB8 Data Sheet, Rev. 3
Freescale Semiconductor
193