83C795 Datasheet, PDF (91/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
LAN CONTROLLER OVERVIEW
Oncethe DMAhas filledtheT ransmit F IF Owith the
las t byteof thepacket, it sets aflag. When theF IF O
becomes empty, it signifies the end of the frame.
CR C computation s tops and the CR C is appended
s erially to the frame, mos t s ignificant bit first.
7.6.7.3 Transmit Underrun
If the F IF O becomes empty before the internal flag
is s et, it is cons idered a transmit underflow and is
posted as a trans mit error in the T rans mit S tatus
(T S T AT ) R egis ter. In this cas e, trans miss ion of the
packet is aborted and an interrupt can be
generated.
7.6.7.4 Early Transmit Underrun Protection
T his feature is us ed to facilitate initiation of
trans miss ion prior to completion of as s embly of the
outgoing frame in the transmit buffer.
E arly trans mit underrun protection is controlled by
twobits in theCommandR egis ter - CMD.DIS E T CH
and CMD.E NE T CH. S etting DIS E T CH to ’1’
dis ables early trans mit underrun checking and
s etting E NE T CH to ’1’ enables checking. Writing
both bits to zero leaves trans mit checking in its
previous s tate. S etting both bits to ’1’is illegal. T his
operation works the s ame as the Command
R egis ter s tart and s top bits for bringing the chip on
and offline.
While early transmit underrun checking is enabled,
the memory address is latched each time the hos t
does a write to the buffer memory (the actual
memory addres s is us ed, not the host addres s).
When the DMA reads packet data from the buffer
memory, the memory address is compared to the
mos t recently-latched memory write addres s
(written from the hos t with E T CHON only). T he
DMAdis tinguis hes between access es todescriptor
table entries and actual packet data.
If early trans mit checking is on, and the DMA’s
memory read addres s is greater than the absolute
value of the latched memory write addres s , a
"buffer underrun" condition is s et. T his condition
aborts the trans mitter which in turn aborts theDMA.
T he condition is cleared when the DMAdetects the
abort and clears the trans mit FIFO. T he transmit
abort is reportedas though it wereaF IF O underrun
and both the T S T AT.UNDE R and INT S T AT.R XE
flag bits are s et.
7.6.7.5 Collisions
When a collision is reported on the CD pin, the
trans mitter sends a 32-bit sequence compos ed of
all ’1’ bits as a jam signal, then terminates its
tr ans mis s ion. If collis ion occur s dur ing the
preambleof aframe, theremainder of thepreamble
is s ent before s ending the jam signal.
If the collision occurred after the end of one s lot
time, transmis sion is aborted without retry after
s ending a jam pattern. T his is cons idered an
out-of-window collision andpos ts as tatus bit in the
T S T AT regis ter (T S T AT.OWC) and is a contributor
to the T XE flag in the INT S T AT R egis ter.
F or collisions that occur within the first slot time of
a frame, a counter of retries is incremented and
checked agains t the retry limit (16). If the number
of retries is les s than the limit, a back-off delay (in
units of s lot-time) is chos en at random. T he
tr ans mi tter then r eques ts the fr ame’s
retransmis sion from memory and delay is initiated.
T he DMA controller clears out the transmit F IF O,
loads its pointer tothestart of framein memory, and
waits for the abort s ignal to s ubside. T he F IF O is
loaded in the same manner as it was initially. If the
maximum number of collis ions (16) is exceeded,
trans miss ion is aborted without further retries and
no back-off delay is executed.
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