83C795 Datasheet, PDF (32/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
Bits 24-31: LN24-LN31
In normal us e, LN24-LN31 is part of theuniqueLAN
address for each adapter (LN47-LN24) andmay be
as signed at the time of manufacture for the end
product.
Bits 32-39: LN32-LN39
In normal us e, LN32-LN39 is part of theuniqueLAN
address for each adapter (LN47-LN24) andmay be
as signed at the time of manufacture for the end
product.
Bits 40-46: LN40-LN46
LN40-LN46 forms part of theuniqueLAN address for
each adapter (LN47-LN24) and may be assigned at
the time of manufacture for the endproduct.
Bit 47: LNMSB
LNMS B is themost significant digit of theuniqueLAN
address block which comprises LN24 through LN47.
5.1.10 BDID - Board ID Register
R ead Port = OE S WH=0
T his regis ter is s imilar to the LAN regis ters except
that it contains an 8-bit code identifying the board
type for software purposes . T he adminis tration of
this ID byteis beyondthes copeof this specification.
T his regis ter is stored and recalled along with the
LAN regis ters.
BIT
7
6
5
4
3
2
1
0
BDID
BDID7
BDID6
BDID5
BDID4
BDID3
BDID2
BDID1
BDID0
RESET INIT
0
EE
0
EE
0
EE
0
EE
0
EE
0
EE
0
EE
0
EE
RECALL
EE
EE
EE
EE
EE
EE
EE
EE
5.1.11 CKSM - Checksum Register
R ead/Write Port = OF S WH=0
Before storing a LAN address, CKS M should be
programmed with an 8-bit checksum which causes
the 2’s complement sum of all eight second-group
register contents to be FFH. T he sum must include
this register. T his register is storedandrecalledalong
with the LAN registers. It is recommended that on
recall of the LAN address, the register’s integrity
s hould be confirmed by computing (in s oftware) the
checksum of the second group of registers.
BIT CKSM
7 CHK7
6 CHK6
5 CHK5
4 CHK4
3 CHK3
2 CHK2
1 CHK1
0 CHK0
RESET
1
1
1
1
1
1
1
1
INIT
EE
EE
EE
EE
EE
EE
EE
EE
RECALL
EE
EE
EE
EE
EE
EE
EE
EE
Bits 7-0: CHK7-CHK0, Checksum Register
T he 83C795 stores the checks um amount in this
regis ter for reference andcomparis on with theLAN
regis ters’ amounts .
5.1.12 GCR2 - General Control Register 2
R ead/Write Ports = 08 S WH=1
T his regis ter is us ed to hold general control
information.
BIT
7
6
5
4
3
2
1
0
GCR2
—
—
—
—
—
—
—
PNPIOP
RESET
0
0
0
0
0
0
0
0
INIT
0
0
0
0
0
0
0
0
Bit 0: PNPIOP, PNP and I/O Mapped Pipe
T his bit is us edtocommunicatetothePlugandPlay
logic that the adapter uses the I/O-mapped mode.
When PNPIOP = 1, the PlugandPlay R AM Control
regis ters are dis abled and the R OM Control regis -
ters are moved from 48h–4Ch to 40h–44h.
5.1.13 IAR - I/O Address Register
R ead/Write Port = 0A S WH=1
T his regis ter programs thebas eI/O addres s for the
chip.
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