83C795 Datasheet, PDF (41/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
Bit 3: TXEE, Transmit Error Enable
When T XE E = 1, this bit enables T rans mit E rror as
defined by the T XE bit in the Interrupt S tatus R eg-
is ter. (S ee the next regis ter, INT S T AT.)
Bit 2: RXEE, Receive Error Enable
When R XE E = 1, this bit enables R eceive E rror as
defined by the R XE bit in the Interrupt S tatus R eg-
is ter. (S ee the next regis ter, INT S T AT.)
Bit 1: PTXE, Packet Transmitted Enable
When T XE E = 1, this bit enables Packet T rans mit-
ted as defined by the PT X bit in the Interrupt S tatus
R egis ter. (S ee the next regis ter, INT S T AT.)
Bit 0: PRXE, Packet Received Enable
When PR XE = 1, this bit enables Packet R eceived
as defined by the PR XE bit in the Interrupt S tatus
R egis ter. (S ee the next regis ter, INT S T AT.)
5.2.14 INTSTAT - Interrupt Status Register
Normal Map R ead/Write Port = 0:17
Linked-List Map R ead/Write Port = 0:17
T he Interrupt S tatus R egis ter enables the hos t to
determine the caus e of an interrupt andto evaluate
pending or mas ked interrupts . Mas ked-out
interrupts are visible in this regis ter although they
will not generate an IR Q to the hos t. Pending
interrupts can be cleared by writing ’1’ to the
as sociated bit of this regis ter. T he IR Q s ignal is
active as long as any unmas ked interrupt bit
remains s et. F or more details , see page 80.
BIT
7 RST
6 ERW
5 CNT
4 OVW
3 TXE
2 RXE
1 PTX
0 PRX
INTSTAT
RESET
1
0
0
0
0
0
0
0
Bit 7: RST, Reset Status
T his bit is s et by 83C795 when its T rans mit and
R eceive s ections are s topped in res pons e to the
as sertion of the R E S E T pin or the s etting of the
CMD.S T P bit. T he R S T bit does not generate an
interrupt.
Bit 6: ERW, Early Receive Warning
When this bit is s et it indicates that the number of
bytes received in the current frame has exceeded
the programmable limit of the E R WCNT register.
Bit 5: CNT, Counter Overflow
When this bit is set it indicates that the MS B of one
or more network error counters has been set.
Bit 4: OVW, Overwrite Warning
T his bit is s et when the receive DMA mus t abort
frame reception due to a lack of receive buffers .
Bit 3: TXE, Transmit Error
T his bit is set when exces sivecollis ions , out-of-win-
dow collisions , F IF O underrun, or early transmit
addres s violations prevent trans mis s ion of a
packet.
Bit 2: RXE, Receive Error
T his bit is s et when apacket is receivedwith one or
more of the following errors :
• CRC error (happens when SEP is enabled)
• Frame alignment error (happens when SEP is
enabled)
• FIFO overrun
• Missed packet (monitor mode)
T his interrupt will not be pos ted if a DMA Abort
occurs, a condition indicated by the as sertion of an
OVW interrupt. If R XE is previous ly s et, it will not
be changed due to OVW.
Bit 1: PTX, Packet Transmitted
T his bit is s et when apacket is trans mitteds ucces s -
fully. When the bit E NH.E OT INT is s et in Multiple
Packet T ransmit mode (see page 5-26), setting of
this interrupt is deferred until the entire transmit
chain has been process ed. PT X is then s et if any
packet in the chain was trans mitteds ucces sfully, or
if a zero length trans mit chain was proces s ed.
Bit 0: PRX, Packet Received
When PR X = 1, it indicates that a packet was
received with no errors .
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