83C795 Datasheet, PDF (45/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
Bit 3: GROUP, Receive Multicast Frames
When GR OUP = 1, this bit enables reception of all
frames that:
• have multicast addresses
• pass the multicast address hashing filter
Bit 2: BROAD, Receive Broadcast Frames
When BR OAD = 1, this bit enables reception of all
frames having a Broadcas t (all ’1’s ) des tination
address .
Bit 1: RUNTS, Receive Runts Frames
When R UNT S = 1, this bit allows reception of
frames having les s than 64 bytes , provided that
they otherwis e meet the requirements of the 802.3
protocol.
Bit 0: SEP, Save Errored Packets
When S E P = 1, it directs the receive unit to s ave
packets having CR C or frame alignment errors in
the buffers .
5.2.24 RDOWNH - Buffer Room Remaining
High Register
Linked-List Map R ead/Write Port = 2:19
T his regis ter contains the upper 8 bits of a regis ter
pair us ed by the DMA controller as a scratch pad
for the buffer room remaining count during the
reception proces s .
Note
Writing to these registers while commu-
nication is taking place may cause er-
rors in the DMA process.
BIT
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A09
0 A08
RDOWNH
RESET
X
X
X
X
X
X
X
X
5.2.25 RDOWNL - Buffer Room Remaining
Low Register
Linked-List Map R ead/Write Port = 2:18
T his regis ter contains the lower 8 bits of a regis ter
pair us ed by the DMA controller as a scratch pad
for the buffer room remaining count during the
reception proces s .
Note
Writing to these registers while commu-
nication is taking place may cause er-
rors in the DMA process.
BIT
7 A07
6 A06
5 A05
4 A04
3 A03
2 A02
1 A01
0 A00
RDOWNL
RESET
X
X
X
X
X
X
X
X
5.2.26 REND - Receive Buffer End Register
Linked-List Map R ead Port = 2:12 Linked-Lis t Map
Write Port = 0:12
T his regis ter holds the upper 8 bits of the firs t
addres s beyond the end of the receive buffer
descriptor table. T he lower 8 bits are as s umed to
be zero. T he table lies between the numbers
(R BE GIN * 256) and (R E ND * 256 - 1). R efer to
page 88 for more details .
BIT
7 RE15
6 RE14
5 RE13
4 RE12
3 RE11
2 RE10
1 RE9
0 RE8
REND
RESET
X
X
X
X
X
X
X
X
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