83C795 Datasheet, PDF (65/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
HOST INTERFACE SECTION
with fast (35 ns ec) R AMs . F or more details , s eethe
AC timing s pecs in S ection 10.
6.6 INTERRUPT REQUEST CONTROL
LOGIC
T here are two s ources of interrupt reques ts to the
host: the LAN Controller and a programmable bit
(S INT ) in the ICR regis ter. T he LAN controller
s ection provides for the mas king, polling, and
clearing of its individual interrupt conditions . T he
s um of the masked LAN interrupt conditions is
’OR ’ed with the programmable interrupt from the
host interface section (S INT ) and gated by the E IL
bit from the ICR regis ter prior to turning on one of
the s even program-s electable tri-state drivers . T he
driver s election is madeviabits in theGCR register.
Interrupt dis abling s hould be accomplis hed via the
ICR .E IL bit, not by changing the interrupt level to
’0’, becaus e during the transition from an active
level to tri-s tate, fals e interrupts may be generated.
T he Interrupt R equest Control logic is depicted in
F igure 6-5.
FIGURE 6-5. INTERRUPT CONTROL LOGIC
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