83C795 Datasheet, PDF (90/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

LAN CONTROLLER OVERVIEW
83C795
7.6.6 Timers
7.6.6.1 Slot Timer
During trans mit, the s lot timer s tarts counting once
the receiver recognizes that a carrier is pres ent at
the start of areturningpreamble. When backingoff,
the s lot timer s tarts with the end of T XE for the
collided frame and does not get reset by any other
incoming frames .
S l ot ti me i s pr ogr ammabl e thr ough the
E nhancement R egis ter. T he choices are 256-,
512-, and 1024-bit times . T he default value is
512-bit times .
7.6.6.2 Backoff Timer
After a trans mis s ion is terminated becaus e of a
collis ion, a retrans miss ion is attempted. T iming of
it is determinedby the’truncatedbinary exponential
backoff’ algorithm. T his algorithm is :
draw random integer r: 0 <= r < 2**k
wherek equals thenumber of retries already onthis
trans miss ion. K s tarts at 0. Wait ’r’ number of s lot
times and then s tart normal trans mit deferral.
T he backoff timer is a 12-bit counter that is
initialized to a random number when an attempted
trans mis s ion res ults in a collision. T he counter
decrements once per slot time until it reaches zero.
T he T ransmit Protocol S tate machine utilizes this
timer to insert a variable amount of delay ahead of
its attempt to retrans mit the frame.
T here is as electable enhancement to backoff timer
operation which caus es it to s us pend counting
while there is network activity and res ume during
idle times. In this mode of operation, the backoff
timer continues to operate while a carrier s ense
remains from the initial collis ion but does not
operate during any other carrier indication. T his is
referred to as the ’S top Backoff’ algorithm. It may
put s tations that us e it at a dis advantage when
operating on the s ame network with s tations not
utilizing it and caution in its use is advised. T his
algorithm can be enabled by s etting the S BACK bit
in the E NH R egis ter.
7.6.6.3 Collision Counter
All retransmis sion attempts are counted by the
collis ion counter. After the maximum number of
attempts is reached (16), the trans mis s ion of the
frame is aborted, an interrupt is generated and
event is reported as an error in the trans mit status
regis ter.
7.6.6.4 Heartbeat Detection
After each transmis sion, the trans mit logicopens a
window 3.6 µs ec long during which it looks for a
puls e on the XCOL s ignal. T his puls e is normally
generated by the MAU and is received through the
AUI interface. If the pulse is received, the CDH
s tatus bit of the T S TAT R egis ter is cleared. If no
puls e is received during the window, the CDH bit is
s et.
7.6.7 Transmitter Operation
7.6.7.1 Transmission Initialization
Packets tobetransmittedarebuilt in buffer memory
by the host. T hes e packets must include the DA,
S A, and data fields. CR C is not read from buffer
memory unles s CR C generation is dis abled.
T he trans mitter reques ts the frame from the DMA
when the T XP bit of the CMD R egis ter is s et by the
host. T he T S T ART and T CNT R egis ters mus t be
properly programmed prior to s etting T XP.
Once set by the hos t, T XP can be cleared only by
the DMA after the trans mitter has s ignalled
completion of an attempted trans mis s ion.
7.6.7.2 Transmission Process
T he DMA s tarts to fill the transmit F IF O with burs ts
of data then notifies the trans mitter that it is ready
for transmis sion. T he trans mitter defers until the
media is clear and an interframe gap has pas s ed
then generates preamble and S FD fields . It then
pulls bytes outof thetrans mit FIFO, s erializes them,
and s hifts bits to the output pins while computing
the CR C on the packet. T heDMAalso monitors the
amount of room remaining in the F IF O andinitiates
a burs t of memory trans fers when there is enough
room for the entire burs t to fit.
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