83C795 Datasheet, PDF (77/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
HOST INTERFACE SECTION
s amemanner (for both reads andwrites ) as theres t
of the E E R OM contents, except that E A[4] (E E R .5)
mus t be s et.
6.8.5 Configuring As A Boot Card
Many LAN adapters are configured as boot cards .
S ince thes e cards must be vis ible to the BIOS at
boot time, they may have to beactivatedbeforethe
PnP s oftware has had a chance to run. T he
PNPBOOT bit (IAR .0) was implemented to do this .
When this bit is readout of E E R OM as s et, the chip
becomes active on the IS Abus . T his bit als oforces
bit 0 of the IAR regis ter to ’1’ which identifies the
card as a boot card to the PnP s oftware.
6.8.6 Configuring With An I/O-Mapped Pipe
When the 8 3 C7 95 i s confi gur ed wi th an
I/O-mapped pipe ins tead of s hared memory, the
board will not use any memory addres s s pace for
the buffer R AM. T herefore, the PnP R AM control
regis ters (us ually locations 40h–44h) are not
neces s ary. If this card requires a R OM, then the
descriptor for the R OM memory window will be the
firs t one in the res ource s tring. T his requires that
the PnP R OM control registers be re-mapped from
48h-4Ch to 40h-44h. T his is accomplis hed by
s etting the PNPIOP bit (GCR 2.0). T his bit mus t be
read out of E E R OM because it must have the
correct valuebeforethechipis activatedby thePnP
logic. S etting this bit als o caus es locations
48h-4Ch to read as zeroes .
6.9 EXTERNAL POWER SUPPLY CONTROL
T he GPOUT pin can be used to control an external
power s upply s upporting a 10Bas e2 MAU circuit.
T his pin can be used to s ource either a simple DC
control s ignal or apuls etrain. T heDCs ignal is us ed
to enable or dis able a controllable power supply.
Note
The DC signal’s polarity on the 83C795
is the opposite of the 83C790’s.
T he puls e train is designed to be the switching
control signal for a s pecific design of switching
power s upply. T he puls e train includes a start-up
s equence as well as a choice of two normal
operating pulse trains .
Before theGPOUT pin can emit apuls etrain, ins tall
the INIT 5 jumper to pull down the MA5 pin. T he
INIT 4 jumper determines which of the two pulse
trains is emitted. T he puls e train is turned on or off
us ingtheGCR .GPOUT bit(s eepage21 for details).
T he puls e train is a 312 KHz signal with 1/8 duty
cycle for the firs t 1024 clocks after GPOUT is
enabled. T his is followed by 1/4 duty cycle for 1K
clocks , 3/8 duty cycle for 1K clocks , and 1/2 (50% )
duty cycle thereafter.
Ins tallation of theINIT 4 jumper caus es thefinal duty
cycle to be 17/32 (53% ) ins tead of 1/2.
6.8.7 Buffer Memory Limitations
Normally, buffer memory can be located above the
1MB DOS limit by s etting the buffer addres s line
(LA23-LA20) decoder to match at ’F’ rather than
zero (done by s etting the HR AM bit, R AR .7). T his
is not s upported by the P nP hardware as
implemented in the 83C795.
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