83C795 Datasheet, PDF (34/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
Bit 7: FINE16, Fine Decode
When F INE 16 = 1, ME M16CS ’s res pons e is gen-
erated only when the actual R AM window is being
address ed. It includes S A16-S A13 in the address
decoding proces s . S ee page 51 for more details .
Bits 5-4: BIOSZ1-BIOSZ0, ROM Window Size
Field
T hes e two bits determine the R OM window size
and are decoded in this manner:
SZ1
0
0
1
1
SZ0
0
1
0
1
ROM Window Size
8K
16K
32K
Disabled
TABLE 5-6. ROM WINDOW SIZE FIELD
Bits 6, 3-0: BA17, BA16-BA13, Base Address
Field
T hes e bits form part of the bas e addres s for the
R OM decoder along with the fixed value of ’11’ for
BA19-BA18. When S A19-S A13 has a value be-
tween this base addres s and the bas e plus the
window s ize and S ME MR are active, a reques t for
the R OM is recognized. A chips elect will be gener-
ated to the R OM if not dis abled. Memory acces s at
the s ame addres s is blocked if R OM is enabled.
5.1.16 GCR - General Control Register
R ead/Write Port = OD S WH = 1
T his register controls interrupt level s election, zero
wait state res pons e, and s everal other functions .
BIT
GCR RESET INIT RECALL
7
XLENGTH 0
0 EE
6
IR2
0
0 EE
5
ZWSEN 0
0 EE
4
RIPL
0
0 EE
3
IR1
0
0 EE
2
IR0
0
0 EE
1
GPOUT 0
0 EE
0
LIT
0
0 EE
Bit 7: XLENGTH, Extended Length Bit Enable
When XLE NGT H = 1, the extendedlength option is
enabled as s pecified by the 802.3 s pecification
(refer to page 69).
Bit 5: ZWSEN, Zero Wait State Enable
T his bit is s et to 1 to enable the chip to generate a
Z WS response when the R AM is acces sed and
available to the hos t.
Bit 4: RIPL, Software Flag
Bits 6, 3-2: IR2-IR0, Interrupt Request Field
T hes e bits form an encoded field to s elect through
which IR Q pin the interrupt output is channeled.
Becaus e of Plug and Play logic, it is neces sary to
connect the interrupt pins to s pecific lines on the
IS Abus , as s hown below. T heinterrupt reques t pins
and their corresponding IS A lines are decoded in
this fas hion:
IRQ2
0
0
0
0
1
1
1
1
IRQ1
0
0
1
1
0
0
1
1
IRQ0
0
1
0
1
0
1
0
1
IRQ Pin
Selected
None
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
ISA Bus
Line
None
IRQ2/9
IRQ3
IRQ5
IRQ7
IRQ10
IRQ11
IRQ15
TABLE 5-7. INTERRUPT REQUEST FIELD
Bit 1: GPOUT, General Purpose Output
T his bit controls the GPOUT pin of the chip. When
GPOUT = 1, it caus es the GPOUT pin to drive low.
In s ome s ys tems , this bit is wired to a s hutdown
control input for DC/DC is olatedpower s upply us ed
in 10Bas e2 applications . For more information on
this feature, refer to S ection 6.7.
Bit 0: LIT, Link Integrity Test
T his bit controls the Link Integrity Tes t. In S TAR -
LAN-10 networks, the Link Integrity Tes t s hould be
dis abled.
LIT = 0 - Link Test is Disabled
LIT = 1 - Link Test is Enabled.
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