83C795 Datasheet, PDF (27/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
5.1 HOST INTERFACE INTERNAL
REGISTERS
T he following s ection des cribes the contents of the
Hos t Interface Internal regis ters. T his regis ter s et
cons is ts of 24 regis ters arrangedin three groups of
eight. T hes e three groups are the LAN Address
regis ters , the Hardware Configuration regis ters
(which write to andreadfromthe E E R OM), andthe
Hardware Control registers . T he S witch R egis ter
bit (HWR .S WH) determines whether the LAN
Addres s R egis ters (S WH = 0) or the Hardware
Configuration R egisters (S WH = 1) are vis ible at
any one time. (S ee HWR - Hardware S upport
R egis ter on page 16 for more information on this
bit.) T he Hardware Control regis ters (including the
CR , E E R , HWR , BPR , ICR , andR E V regis ters) are
always visible.
B its within regis ters may als o have different
functions dependingon whether they are readfrom
or written to.
T hroughout this s ection, certain terms are used to
describe each regis ter and are defined below:
Term
Definition
RESET
INIT
RECALL
Value During RESET Time
If the INIT3, 2, 1, 0 jumpers = 1001,
this value is loaded into the register
immediately after RESET TIME.
Some of these values are forced by
hardware and others are recalled
from EEROM. Recall time is on the
order of 2 msec. While the initial
recall is ongoing, register may have
either the RESET or INIT values
This value is loaded when a recall is
performed other than after a RESET.
REGISTER Possible register values are:
VALUES
1 = logical 1
0 = logical 0
PIN = value unknown or
wired to external pin.
EE = value loaded from
EEROM.
— = not used.
TABLE 5-4. REGISTER TERM DEFINITIONS
5.1.1 CR - Control Register
R ead/Write Port = 00
T his regis ter has control over buffer memory
enabling and s oft res et of the LAN controller.
BIT
CR
7 RNIC
6 MENB
5—
4 CR4
3 CR3
2 RP15
1 RP14
0 RP13
RESET
1
0
0
0
0
0
0
0
Bit 7: RNIC, Reset Network Interface Controller
S et R NIC to 1 then back to 0 to force a hardware
res et to the LAN Controller.
Bit 6: MENB, Memory Enable
S et ME NB to 1 to enable hos t acces s to s hared
memory.
Bit 4-3: CR4-CR3, Reserved For Increase In RP
Field
Bit 2-0: RP15-RP13, RAM Offset
A buffer addres s is created by adding the contents
of this field to the difference between the buffer
base addres s and the addres s s upplied by the
S A19-S A00 lines . T his sumis treatedas amovable
page offs et which is then ins erted into the buffer
window. T his offs et values houldonly beus edwhen
the memory provided is larger than the window
s elected.
5.1.2 EER - EEROM Register
R ead/Write Port = 01
T his regis ter controls the s tores to andrecalls from
E E R OM. In addition, four input pins are vis ible
through this regis ter. S ome bits have different
functions when read than when written.
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