83C795 Datasheet, PDF (84/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

LAN CONTROLLER OVERVIEW
83C795
Operating in ALT E GO mode engages a second
improvement to the reception proces s . T he
receiver checks for corruption of the preamble and
terminates reception of any frame which has
cons ecutive ’0’ bits . All valid preambles have an
al ter nati ng ’1 0 ’ patter n fol l owed by the
S tart-of-F rame delimiter (’11’). T he above is
checked immediately on the as s ertion of the
internal carrier s ens e without any grace periods .
Neither of thes e causes for abort forces logicto s et
R XE .
7.4.5 CRC Checker
T he R eceiver computes the CR C of an incoming
frame serially. CR C computation includes addres s ,
data, and CR C frame fields . It excludes preamble
andS F D. Computation s tops after reception of las t
whole octet followinglos s of carrier. T he final value
of the CR C mus t be "C704DD7B" for the packet to
be validated.
T he CR C polynomial us ed is AUT ODIN II:
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10
+ X8 + X7 + X5 + X4 + X2 + X1 + 1.
If the received frame’s CR C does not check out, a
CR C error is indicated in the S tatus R egister and
the CR C E rror Counter is incremented. F rame
r ecepti on wi l l ter mi nate unl es s the
R eceive-with-E rrors mode is enabled. In addition,
if thenumber of bits receivedin the las t octet (when
the carrier is terminated) is greater than one and
les s than 8 (a full octet), and the CR C check for all
complete octets fails , the frame is als o labeled as
an ’alignment error’ and an error flag is s et in the
S tatus R egis ter; if this occurs , the Alignment E rror
Counter will be incremented.
7.4.6 Address Recognition Logic
Des tination addres s es that are ’individual’ are
compared to a 6-byte s tation addres s s tored in
regis ters. If all bits match or if the PR OMIS CUOUS
mode is enabled, the frame is received.
A snapshot is taken of the partially-computed CR C
as the end of the des tination field pas s es through
the CR C checker. If the addres s has the ’group’ or
’multicast’ bit s et, 6 bits of this checks um are us ed
as a has hed index to a 64-bit Multicas t F ilter table.
If reception of multicas t frames has been enabled
andif the6-bit partial CR C points toabit in thetable
that has been turnedon, the multicas t frame will be
recognized. Broadcas t frames are received when
the Broadcast E nable bit (R CON.BR OAD) is active
or when the hashed bit in the Multicast F ilter table
has been s et.
To caus e promiscuous reception of multicas t and
broadcas t frames , the entire Group Addres s table
s hould be turned on and reception of multicas t
frames enabled.
If the addres s is rejected, the frame is als o rejected
and none of the frame is trans ported to the buffer
memory. If the addres s is recognized, buffering of
the frame begins .
7.4.7 Received Byte Counter and Early
Receive Warning Interrupt
T his circuit counts the number of bytes in each
completed frame and filters out runt frames (less
than 64 bytes) unles s the runt filter is defeated by
s etting the Accept R unt bit in the R eceive
Configuration R egis ter (R CON.R UNT S ).
T he E arly R eceive Warning (E R W) interrupt is
generated when the received byte count equals or
exceeds a value specified in the E arly R eceive
Warning Count R egis ter (E R WCNT ). T he value of
E R WCNT is left-s hifted four bits (multiplied by 16)
before it is comparedto thereceivebyte count. T he
value is 8 bits wide, allowing the E R W thres hold to
be s et between 0 and 4K with a res olution of 16
bytes .
T he E R W interrupt is only generated if an active
reception is in progres s. Once an early receive
interrupt has been set, it may be cleared and will
not be s et again until another packet exceeds the
E R W thres hold or the E R WCNT R egis ter is written
to. Writinga value to E RWCNT that is les s than the
current receive byte count (while reception is in
progres s ) will automatically s et the E R W interrupt.
T heE R W interrupt is mappedtobit 6 in theInterrupt
S tatus R egis ter (INS T AT ). T he E RW interrupt is
enabled or disabled like all other interrupts by the
corres ponding bit in the Interrupt Mas k R egis ter
(INT MAS K).
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