83C795 Datasheet, PDF (72/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

HOST INTERFACE SECTION
83C795
Any writes to the ADDR E S S port that do not match
the Initiation Key s equence will caus e the logic to
res et back to the s tart of the Key. While the PnP
s tatemachineis in theWaitForKey state, all access
to the R E AD_DAT A or WR IT E _DAT A ports is
dis abled.
Once the state machine is in the S leep s tate, the
board res ponds to a WAKE [CS N] command. E ach
PnP board has a regis ter to s tore a Card S elect
Number, and this regis ter contains a z ero at
power-up. T he card res ponds to a WAKE [CS N]
commandonly if theCS N in thecommandmatches
the value in the Card S elect Number regis ter. If the
card’s CS N does not match the CS N in the
WAKE [CS N], it goes into the s leep s tate. T he card
s tays in the s leep state until awakened by the
correct WAKE [CS N]. If the CS N is zero, then the
card enters the Is olation s tate, otherwis e it moves
into the Configuration s tate.
6.8.2.1 Isolation
A s imple algorithm is us edto is olate each Plug and
Play card. T he is olation protocol requires that each
card contain a unique number, referred to as the
s erial identifier. T his is a 72-bit number compos ed
of two 32-bit fields andan 8-bit checks um. T hefirs t
field is a vendor identifier. T he s econd can be any
value- for example, as erial number or part of aLAN
address . T henumber is acces s eds erially, bit by bit,
by the isolation logicand is us ed to differentiate the
adapters .
T he PnP software begins the isolation by s ending
out a Wake[0] command. T his will caus e all PnP
cards that havenot been is olatedtotrans ition tothe
Is olation state. If this is the first pas s through the
protocol, then the s oftware will pick an initial
location for the R E AD_DATA port at this time. T he
s oftware then is s ues two reads to the IS OLAT ION
regis ter for each bit in the s erial identifier. If the
current bit is a ’1’, then the PnP board is expected
to return 0x55 on the first read, and 0xAA on the
s econd. If the current bit is a ’0’, then the PnP logic
will drive nothing on the bus , but will ins tead
observe the bus to s ee if another cardis drivingthe
0x55, 0xAA pattern. If it does s ee that pattern for
the two reads , then that card mus t put its elf back
intotheS leeps tate. T his ens ures that only onePnP
card will be in the Is olation s tate at the end of the
protocol.
T he PnP s oftware will recognize the 0x55, 0xAA
pattern as a ’1’ for that bit position, and any other
pattern as a ’0’. Once all 72 bits have been read,
the PnP software will then verify that the checks um
matches the data. If it does , then the s oftware will
as sign aunique, non-zero CS N tothe one cardthat
made it to the end of the protocol. T his will cause
that one card to trans is tion to the Configuration
s tate. If the checks um does not match, then the
s oftware will move the location of the R E AD_DAT A
port, and s tart the protocol over.
6.8.2.2 Configuration And Activation
T he Is olation protocol ens ures that only one card
can be in the Configuration s tate at a time. T his
makes it poss ible to read out the res ource s tring
byte-s erially when in this s tate. T his is donethrough
the R es ource_Data R egister (location 0x04), after
polling the status bit (location 0x05, bit 0) to make
s ure the data in the regis ter is valid. T he PnP
s oftware will us e this method to read the entire
res ource s tring from the PnP card. T his s tring lis ts
the res ource requirements of the card, along with
what the cardis capable of us ing(s ee s ection 6.8.5
for more on the res ource s tring). T he s oftware
repeats this process with all of the PnP cards in the
s ystem, and thus obtains an image of all of the
res ource requirements in the sys tem. T he s oftware
then arbitrates the available res ources to meet the
needs of each card. If aconfiguration can be found,
then the ass igned configuration for each card will
be written to the cards . T he s oftware then activates
the card by s etting the Activate bit (location 0x30,
bit 0). On the 83C795, this caus es the s oftware to
trans fer the appropriate s ettings in the P nP
confi gur ati on r egi s ter s to the 8 3C79 5’s
configuration regis ters by way of as hift chain. Once
this transfer is complete, the res t of the logicin the
83C795 becomes active.
6.8.3 Configuration Registers
F igure 6-8 contains a map s howing all of the
configur ation regis ters implemented by the
83C795. T his figure also illustrates the relationship
between the auto-configuration ports , the PnP
s econdary addres s s pace, andthe res ource string.
Mos t of the configuration regis ters can only be
acces s ed when the PnP s tate machine is in certain
s tates . Any unus ed regis ters or bits in the PnP
regis ter s pace mus t return zeros when read. T he
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