83C795 Datasheet, PDF (35/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
Dis abling the Link Integrity Tes t (LIT ) forces the
83C795 to s elect the twis ted-pair interface. When
LIT is enabled, the twisted-pair interface will be
automatically s elected when link activity is found
and the AUI interface will be selected when the
twisted-pair link enters the10BAS E -T link fail s tate.
5.1.17 ERFAL - Early Receive Fail Address
Low Register
R ead/Write Port = OE S WH = 1
T his regis ter contains the lower eight bits for the
address at which the early-receive logic detected
an underrun. T his register als o contains a control
bit for the Plug and Play logic.
BIT
7
6
5
4
3
2
1
0
ERFAL
ERFA7
ERFA6
ERFA5
ERFA4
ERFA3
ERFA2
—
PNPEN
RESET
—
—
—
—
—
—
0
1
RECALL
—
—
—
—
—
—
0
EE
Bits 7-2: ERFA7-2, Early Receive Failure Address
T his regis ter contains the lower eight bits of the
address where the early receive logic detected an
underrun. T he comparis on has a granularity of 4
bytes s o the leas t s ignificant two bits are zero. T his
value is read-only.
Bit 0: PNPEN, Plug and Play Enable
When PNPE N = 1 along with the ins tallation of
JUMPE R 6, Plug and Play logicis enabled. T his bit
is readablebut can only bes et by theinitial E E R OM
load.
5.1.18 ERFAH - Early Receive Fail Address
High Register
R ead/Write Port = OF S WH = 1
T his regis ter contains the higher eight bits for the
address at which the early receive logic detected
an underrun.
BIT
7
6
5
4
3
2
1
0
ERFAH
ERFA15
ERFA14
ERFA13
ERFA12
ERFA11
ERFA10
ERFA09
ERFA08
RESET
—
—
—
—
—
—
—
—
RECALL
—
—
—
—
—
—
—
—
Bits 7-0: ERFA15-8, Early Receive Failure Address
T his register contains the higher eight bits of the
address where the early receive logic detected an
underrun.
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