83C795 Datasheet, PDF (66/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

HOST INTERFACE SECTION
83C795
6.7 EEROM CONTROLLER AND ITS
UTILIZATION
T he 83C795 is des igned to operate in conjunction
with a s erial E E R OM memory that s tores the
configur ation of the hos t interface and the
permanently-as signed LAN s tation addres s . It can
reduce the number of jumpers needed on a board
andallows for reconfiguration without removingthe
board from the s ys tem. T he E E R OM is us ed to
initialize s ome of the hos t interface configuration
regis ters at res et time.
6.7.1 Initialization Of 83C795
Activation of the res et pin forces the internal s tate
of the 83C795 to a known value. T here is a group
of option bits that can be configured by attaching
res is tive pull-downs to four of the memory address
output lines (MA09-MA00). T hes e pins are
s ometimes referred to as the INIT pins . T hey s till
perform their function as memory addres s lines but
als o act as input pins during the R E S E T proces s .
E ach pin has a high impedance internal pull-up
res is tor that caus es the pin to read as ’1’ unles s a
lower-impedanceexternal pull-down resistor brings
the natural s tate of the line to a logic ’0’ level. It is
expected that an application of this chip would use
a s et of jumpers to s electively connect thes e pins
to the external pull-downs , as s hown in Table 6-2
below.
Jumpers Pins
Effect
These jumpers are installed to mark 0 bits
JMP0-3 MA0-3 EEROM Config. field,
bits 0-3.
These jumpers are installed to activate features
JMP4 MA4 Switching PS HIDUTY option.
JMP5
MA5 Switching PS output from
GPOUT.
JMP6 MA6 Plug and Play logic enable.
JMP7 MA7 NEC PC-98 Bus support.
JMP8
MA8 Drive 20 MHz clock out T L E D
pin.
JMP9
MA9 Use 83C790 Chip ID field
instead of the 83C795 ID
field.
TABLE 6-2. JUMPER EXAMPLE
At theendof reset, thes eINIT pins ares ampledand
latched. One of thes e combinations determines
whether the E E R OM is read into the hos t interface
regis ter s . Or dinarily, the 83C795 loads its
configuration regis ters from E E R OM, but s election
of one s pecial combination of jumpers (when all
INIT s are pulled down) provides a means of
bypas s ing the E E R OM load to allow rapid
s imulation and tes ting of the device. Utilize the
bypas s mode to produce a less expensive adapter
des ign which does not retain configuration or
address permanently.
T here is als o a means of accelerating the E E R OM
clock and as s ociated E E R OM interface pins
(E E DO, E E CS , LLE D, R LE D) for tes t purposes .
LLE D is connectedtotheE E R OMclock pin (E E S K)
and is normally the primary clock (20 MHz) divided
down by 128 during E E R OM acces s es. T he IOR
and IOW pins are latched on the ris ing edge of
R E S E T. If both are active (low) at the s ame time,
the clock accelerates to 10 MHz. To res tore the
normal 156 kHz clock rate, the chip is reset without
activating IOR or IOW. R LE D is connected to the
E E R OM’s data-in pin, E E DI.
U nles s bypas s ed, the E E R OM data is read
automatically into the hos t interface regis ters jus t
after the 83C795 is res et. T his takes approximately
2 milliseconds . During this time, memory, R OM,
andregis ter acces s is dis abled. I/Oacces s es toany
host interface regis ter return garbage except for bit
6, which will return ’1’ until the regis ters are loaded
at which time bit 6 returns ’0’. To determine when
the initial load of regis ters is completed, poll the
E E R R egis ter. If the R E CALL bit (Bit 6) equals 0,
the initial load is complete.
T he regis ters s tart out with their res et values and
are changed one regis ter at a time as the E E R OM
is read out. T he buffer memory is always dis abled
upon reset and mus t be enabled by s oftware.
T he first time an E E R OM is powered up, it has
random data. T he 83C795 can be acces s ed at
known initial addres s es if a special s etting of the
INIT pins is chos en when R E S E T pin is active. T his
is explained in more detail in the following s ection.
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