83C795 Datasheet, PDF (37/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
5.2.3 CMD - Command Register
Normal Map R ead/Write Port = X:10
Linked-List Map R ead/Write Port = X:10
BIT
CMD
7 PS1
6 PS0
5 RFU
4 ENETCH
3 DISETCH
2 TXP
1 STA
0 STP
RESET
0
0
0
0
0
0
0
1
T he Command regis ter is us ed to initialize the
83C795 chip, s tart trans mis s ions , and s witch
pages .
Bits 7-6: PS1-PS0, Page Select
T his 2-bit field des ignates which of 4 pages is
s howing. T hey decode as follows:
T he 83C795 clears this bit upon completion or
abortion of the transmis sion.
Bit 1: STA, Start Bit
S et the S T A bit to activate the 83C795 after power
up or when the 83C795 has been res et by a soft-
ware command. Noframes can bes ent or received
until this bit has been s et. T he us er’s s oftware
s hould s et up the other regis ters prior to bringing
the device on line, but setting this bit is the actual
command which brings the T rans mit and R eceive
portions of the device online. Once set, this bit may
be cleared and the 83C795 will continue to remain
online.
Bit 0: STP, Stop Bit
S et the S T P bit to take the chip offline and dis en-
gage from the LAN. Frames partially trans mitted or
received are completed before res et occurs. INT -
S T AT.R S T is set high when the T ransmit and R e-
ceive s ection have completed all outs tanding
operations (see page 28). No frames will be re-
ceivedor transmitteduntil thes tart bit has been s et.
PS1
0
1
0
1
PS0
0
0
1
1
Page Select
Page 1
Page 2
Page 3
Page 4
TABLE 5-8. PAGE SELECT FIELD
Bit 5: RFU, Reserved for Future Use
T his bit is not us ed by 83C795 and always returns
zero when read.
Bit 4: ENETCH, Enable Early Transmit Checking
By setting this bit to 1, it enables comparis on of
trans mit DMA addres s agains t the hos t memory
write address . Once s et, this bit can beclearedand
the 83C795 continues to check trans mis s ion ad-
dres s es until DIS E T CH is s et. S eepage78 for more
details .
Bit 3: DISETCH, Disable Early Transmit Checking
By s etting this bit to 1, it dis ables the early transmit
address checking. Once s et, the bit can be cleared
and trans mit addres s checking is s uppres s ed until
E NE T CH is s et. S ee page 78 for more details.
Bit 2: TXP, Transmit packet
S et this bit after loading the T rans mit Buffer and
Control regis ters toinitiatetrans mis s ion of apacket.
5.2.4 COLCNT - Collision Count Register
Normal Map R ead Port = 0:15
Linked-List Map R ead Port = 0:15
T his regis ter contains the number of collis ions
detectedwhileattemptingtotrans mit thecurrent (or
mos t recent) packet. It is clearedto zero at the start
of trans miss ion. If no collis ions are detected, the
counter wil l r ead z er o. F or each collis ion
encountered, thecount is incremented. If morethan
15 collisions occur, the abort bit of T S T AT is set and
the count is res et to zero (s ee page 38).
BIT
7 T10
6 T9
5 T8
4 T7
3 CT3
2 CT2
1 CT1
0 CT0
COLCNT
RESET
0
0
0
0
0
0
0
0
Bits 7-4: T10-T7, Backoff Counter
T hes e 4 cons ecutive bits always return zero.
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