83C795 Datasheet, PDF (30/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
5.1.6 BPR - BIOS Page Register
R ead/Write Port = 05
T his regis ter controls mapping of R OM window to
R OM addres s and other mis cellaneous controls.
BIT
BPR
7 M16EN
6 BP15
5 BP14
4 BP13
3—
2—
1 SOFT1
0 SOFT0
RESET
0
0
0
0
0
0
0
0
Bit 7: M16EN, Memory 16-bit Enable
S et M16E N to1 to enable16-bit memory access by
the host. T his s houldbe only s et when all interrupts
have been disabled. S ee page 17 for details.
Bits 6-4: BP15-13, ROM Offset
R OM addres s is created by adding the contents of
this field to the difference between R OM bas e ad-
dres s and the addres s s upplied on the S A19-S A00
lines . T his sum serves as a movable page offs et
into the R OM window. It is intended that the offs et
be us edonly when the R OM providedis larger than
the window s elected.
Bits 1-0: SOFT1-SOFT0
T hes e bits are written and read by s oftware. T hey
may be us ed as ’claim’ bits for allocation of drivers
tomultipleLAN connections within acommon back-
plane.
5.1.7 ICR - Interrupt Control Register
R ead/Write Port = 06
T his regis ter enables andmas ks interrupts . It is not
us edto s elect IR Q lines . T hat function is performed
through the GCR R egis ter.
BIT
ICR
7 MCTEST
6 STAG
5 IOPAV
4 IOPEN
3 SINT
2 MASK2
1 MASK1
0 EIL
RESET
0
0
0
0
0
0
0
0
Bit 7: MCTEST, Memory Cache Test Bit
T he memory cache counters are acceleratedwhen
MCT E S T =1. Us e this bit only for tes t purposes .
Bit 6: STAG, Staggered Address Enable
When S T AG = 1, the lowes t bit in the buffer counter
is forced to 1 on memory cache mis s es.
Bit 5: IOPAV, I/O Pipe Address Visible
When IOPAV = 1, it allows the I/O pipe’s temporary
address register tobereadout of theR E V R egister.
Bit 4: IOPEN, I/O Pipe Enable
When IOPE N = 1, the I/O pipe is enabled. R egular
memory acces s es shouldbe dis abled when this bit
is s et.
Bit 3: SINT, Software Interrupt
S et S INT = 1 to create an interrupt under s oftware
control. S et to zero to remove interrupt. F or more
details , refer to page 52.
Bit 2: MASK2, Mask Interrupt Sources
S et MAS K2 to 1 to mas k out interrupt from the NIC.
Bit 1: MASK1, Not used
Bit 0: EIL, Enable Interrupts
S et to 1 to enable interrupts from this device. T his
enable controls S INT and interrupts from the LAN
controller. F or more details , refer to page 52.
17