83C795 Datasheet, PDF (22/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

PIN LIST
83C795
Mnemonic
T LED
T PR+
T PR-
T PX1+
T PX1-
T PX2+
T PX2-
T X+
T X-
VDD
(14 pins )
VS S
(24 pins )
X1
X2
Z WS
Pin Number I/O
129
O
128
I
127
103
O
102
104
O
101
99
O
98
22, 41, 42,
47, 53, 59,
67, 68, 81,
82, 105,
111, 116,
119, 120,
134, 135,
159, 160
1, 2, 11, 21,
27, 39, 40,
50, 56, 62,
66, 70, 79,
80, 89, 92,
94, 100,
114, 121,
122, 133,
136, 147
96
I
97
O
91
O
Description
T R ANS MIT LE D DR IVE R . When on, T LE D drives low to turn on
an external LE D. When there is no trans mis s ion (T XE inactive),
T LE D is off. When data is trans mitted, T LE D goes active for
approximately 50ms longer than the trans mitted packet length.
T LE D does not go active for Link Tes t puls es. T his pin also s erves
as the s can data output (formerly S CANOUT ) in scan mode, or as
a 20 MHz buffered clock output if JUMPE R 8 is ins talled.
T WPR R E CE IVE . In 10Bas eT operation, Manches ter encoded-
data are received via T PR + /T PR -. T hey are connected to the
twis ted pair medium through a transformer and filter.
T WPR T R ANS MIT. T PX1+ and T PX1- are used for 10Bas eT only.
T hey are the high current pos itive and negative output pins .
T WPR T R ANS MIT. T PX2+ and T PX2- are used for 10Bas eT only.
T hey are the low current pos itive and negative output pins .
AUI T R ANS MIT. T X+ and T X- transmit differential, Manches ter
encoded data to the trans ceiver. T hes e are current-driving outputs
that furnis h E CL level s ignals when connected to required external
pullup resistors of 150Ω.
+5 VOLT S OUR CE S . S ome are for logic, some power the pin
drivers , and others provide power to the analog portions of the
circuit.
GR OUND. S ome are for logic, s ome power the pin drivers, and
others provide power to the analog portions of the circuit.
CRYS T AL OS CILLAT OR . T he crys tal is attached across thes e two
pins . Must be 20.000 MHz ± 50 ppm. T his clock operates the
chip’s logic and is divided by 2 internally to become the transmit
clock.
PC Z E R O WAIT S TAT E . Active low. Z ero Wait S tate s ignal tells
the microprocess or that it can complete the pres ent bus cycle
without ins erting any additional wait cycles . Z WS is driven by a
tri-s tate driver capable of s inking 24 mA.
TABLE 4-1. 83C795 PIN ASSIGNMENTS (CONT.)
9