83C795 Datasheet, PDF(39/136 Page) List of Unclassifed Manufacturers

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83C795 Datasheet, PDF (39/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

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83C795

ETHERNET SYSTEM CONTROLLER REGISTERS

BIT

7 A07

6 A06

5 A05

4 A04

3 A03

2 A02

1 A01

0 A00

CURRL

RESET

5.2.9 DCON - Data Configuration Register

Linked-List MapR eadPort = 2:1E Linked-Lis t Map

Write Port = 0:1E

T his regis ter always returns 41h. In the83C790 this

regis ter controlledDMAburs t lengths ; however, the

83C795 is hardwired for 8-byte burs ts . R efer to

page 65 for more information.

5.2.10 ENH - Enhancement Register

Normal Map R ead/Write Port = 2:17

Linked-List Map R ead/Write Port = 2:17

T his regis ter enables enhancement features .

BIT

ENH

7â

6â

5 ALTEGO

4 SLOT1

3 SLOT0

2 EOTINT

1â

0 SBACK

RESET

Bits 7-6: Unused

Bit 5: ALTEGO, Buffering Format Selection

ALTEGO = 0 -

Des ignates ring buffering and s ingle frame trans -

miss ion format. T his is es sentially 8390/83C690

compatibility mode.

ALTEGO = 1 -

Des ignates linked-lis t receive buffering and multi-

ple frame trans mis s ion format. T he regis ter ad-

dres s map is s elected with this bit, exposing the

regis ters as sociated with the s elected buffering

mode.

Bits 4-3: SLOT1-0, Slot Time Selection

T his two-bit field s elects the s lot time according to

Table 5-10.

SLOT1

SLOT0

Slot Time

512 bit times (Ethernet)

256 bit times

1024 bit times

TABLE 5-9. SLOT TIME SELECTION FIELD

Bit 2: EOTINT, Interrupt on End-of-Transmit

EOTINT = 1 -

Interrupt on E nd-of-T rans mit chain ins tead of each

trans mittedframe. T his bit is ignoredif not operating

in multiple frame trans mis s ion mode.

EOTINT = 0 -

Interrupt on each trans mitted frame.

Bit 0: SBACK, Enable Stop Backup Modifications

SBACK = 1 -

E nable the S top Backoff modifications to the back-

off timer.

SBACK = 0 -

Normal backoff.

5.2.11 ERWCNT - Early Receive Warning

Threshold Register

Normal Map R ead/Write Port = 0:18

Linked-List Map R ead/Write Port = 0:18

T his register contains the R eceived Byte Count

thres hold at which the E arly R eceive Warning

interrupt is generated. T he E R W interrupt is

generated when R BC â¥ E RW. Bits 3-0 of R BC are

ignored. F or more information on this register, refer

to page 71.

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