83C795 Datasheet, PDF (58/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

HOST INTERFACE SECTION
83C795
FIGURE 6-1. MEMORY CACHE ARRANGEMENT
6.1.1 Zero Wait State Response to Host
T heZ ero Wait S tates ignal tells themicroproces s or
that it can complete the pres ent bus cycle without
ins erting any additional wait cycles . F or 16-bit
memory acces s , this means zero wait s tates are
ins erted by the host bus logicand the access cycle
completes in 2 bus clocks. When as s erted for an 8
bit memory acces s , an IS A bus automatically
ins erts the minimum of 2 wait s tates .
T he response algorithm for the Z WS line depends
upon the memory width, the hos t acces s type and
whether the board has been enabled to act as a
16-bit device. T he appropriate ZWS res pons e logic
is selected on the basis of the BPR .M16E N control
bit and whether the board is in an 8- or 16-bit slot.
T he memory cache can accommodate zero wait
s tate timing if the following conditions are met:
1. The type of host access matches the current
mode of the cache,
3. The cache either contains at least one valid
data word for reads or has room for at least
one more word for writes.
F or writes , zerowait s tates areals oalways poss ible
if the cache is in read mode, or if it is currently
empty.
T here is a Z ero Wait E nable bit in one of the hos t
interfaceregis ters (CR .Z WS E N) which can beus ed
to prevent the 83C795 fromas s ertingtheZ ero Wait
S tate s ignal.
6.1.2 Staggered Address Transfers
S taggered addres s transfers occur when the hos t
attempts 16-bit datatrans fers froms ys temmemory
to the local buffer R AM and finds that the address
of the sys tem data differs from the local addres s in
the leas t significant bit (one is even, one is odd). In
cons equence, the IS A bus forbids 16-bit acces s es
to odd locations and breaks the trans fer into two
8-bit cycles which run cons iderably s lower.
2. The host address matches the value in the
host counter, and
To overcome this on the 795:
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