83C795 Datasheet, PDF (46/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
5.2.27 RSTART - Receive Start Page Register
Normal Map R ead Port = 2:11 Normal Map Write
Port = 0:11
R eceiveS tart Pageregis ter points tothestart of the
receive buffer ring. Only A08-A15 are s pecified
s i nce al l buffer s ar e aligned on 256-byte
boundaries . R efer to page 88 for more information.
BIT
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A09
0 A08
RSTART
RESET
X
X
X
X
X
X
X
X
5.2.28 RSTAT - Receive Packet Status
Register
Normal Map R ead Port = 0:1C Linked-Lis t Map
R ead Port = 0:1C
T his regis ter reports the s tatus of the mos t-recently
receivedpacket. It categorizes any errors that were
detected and reports on the type of addres s
recognized. All bits are cleared at the s tart of
reception except for DIS .
BIT
RSTAT
7 DRF
6 DIS
5 GROUP
4 MPA
3 OVER
2 FAE
1 CRC
0 PRX
RESET
0
0
0
0
0
0
0
0
Bit 7: DFR, Deferring IGSM
T his bit is s et when the Interframe Gap S tate Ma-
chine (IGS M) is deferring. If the transceiver has
as serted the CD line as a result of jabber, this bit
will s tay s et indicating the jabber condition.
Bit 6: DIS, Receiver Disabled
T his bit is s et when the receiver is in Monitor Mode.
It is cleared when the receiver leaves Monitor
Mode.
Bit 5: GROUP, Group Address Recognized
T his bit is s et when the recognized addres s was
either a group addres s (multicas t) or broadcas t. It
is cleared to indicate an individual (physical) ad-
dres s match.
Bit 4: MPA, Missed Packet
T his bit is s et when apacket intendedfor this s tation
cannot be accepted by the device due to a lack of
receive buffers or becaus e the device is in monitor
mode. T he Mis s ed Packet Counter (MPCNT ) is
als o incremented when this occurs .
Bit 3: OVER, FIFO Overrun
T his bit is s et when the receiver attempts to write
intoaF IF Othat is already full. T his occurs when the
DMA fails to keep up with the received data.
Bit 2: FAE, Frame Alignment Error
When FAE = 1, it indicates that theincomingpacket
did not end on a byte boundary and the CR C did
not match at the las t byte boundary. T he Alignment
E rror Counter is incremented when this condition
occurs .
Bit 1: CRC, CRC Error
When this bit is s et, it indicates that the frame’s
computed CR C failed to corres pond with the CR C
appended to the end of the frame. T his error also
caus es the CR C Counter to be incremented.
Bit 0: PRX, Packet Received Intact
When set to ’1’, this bit indicates that a packet was
receivedwithout error. T his means that CR C = FAE
= OVE R = MPA = 0.
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