83C795 Datasheet, PDF (52/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
Bit 6: CDH, Collision Detect Heartbeat
T his bit is s et to a ’1’ during transmis sion of each
packet. It is s et to ’0’ if a collis ion is detected within
3.6 µs ec of the end of each packet transmis sion. If
no collision is detected within this window, it re-
mains ’1’.
Bit 5: UNDERFIFO, FIFO or Buffer Underrun
When this bit is s et, it means either:
• a FIFO underrun condition has occurred. This
condition results when the transmit unit at-
tempts to read from an empty FIFO prior to
receiving the transmit done flag from DMA. This
means that the FIFO failed to supply enough
data for the serializer to maintain frame genera-
tion.
• a Buffer underrun has occurred. This condition
happens when the transmit DMA accesses an
address that is greater than or equal to the most
recent host-written location in memory, pro-
vided that the Early Transmit Check feature is
enabled.
Bit 4: CRL, Carrier Sense Lost
T his bit is s et if the carrier is los t during packet
trans miss ion. Carrier s ense is monitored from its
ris ingedgeat thes tart of theoutgoingframe’s echo.
T ransmis sion is not aborted upon loss of carrier. It
is reported for s tatistical purpos es .
Bit 3: ABORT, Abort Transmission
T his bit is s et if the trans mis s ion is aborted due to
exces s ive collis ions .
Bit 2: TWC, Transmitted With Collisions
T his bit is s et if the frame collidedat leas t once with
another frame on the network. It is not set for either
out-of-window collis ions or exces s ive collis ion
aborts .
Bit 1: NDT, Non-deferred Transmission
T his bit is s et if the frame was transmitteds ucces s -
fully without deferring. A deferred trans miss ion can
only occur the firs t time an attempt is made to s end
apacket. Collis ions arenot deferredtransmis sions .
Bit 0: PTX, Packet Transmitted
T his bit is s et to indicate trans mis s ion of a packet
without exces s ive collis ions or a F IF O underrun.
5.2.46 TTABH - Transmit Buffer Pointer High
Register
Linked-List Map R ead/Write Port = 0:1B
T his regis ter contains the higher 8 bits of the
regis ter pair usedas a pointer to the transmit buffer
des criptors table. T hes e regis ters s hould be
initialized to the same value as T BE GIN when the
des criptor table is created, and not altered
thereafter by the us er unles s the trans mit buffer
pool is rebuilt. F or more information, refer to page
80.
BIT
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A09
0 A08
TTABH
RESET
X
X
X
X
X
X
X
X
5.2.47 TTABL - Transmit Buffer Pointer Low
Register
Linked-List Map R ead/Write Port = 0:1A
T his regis ter contains thelower 8 bits of theregis ter
pair us ed as a pointer to the trans mit buffer
des criptor table. T hes e regis ters s hould be
initialized to the same value as T BE GIN when the
des criptor table is created, and not altered
thereafter by the us er unles s the trans mit buffer
pool is rebuilt.
BIT
7 A07
6 A06
5 A05
4 A04
3 A03
2 A02
1 A01
0 A00
TTABL
RESET
X
X
X
X
X
X
X
X
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