83C795 Datasheet, PDF (19/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
PIN LIST
Mnemonic
AE N
B AL E
BS R
CAP
CD+
CD-
E E CS
E E DO
GPOUT
HOS T CLK
IO16CS
IOR
IOR DY
IOW
IR Q1
IR Q2
IR Q3
IR Q4
IR Q5
IR Q6
IR Q7
Pin Number I/O
93
I
29
I
115
I
113
I
126
I
125
132
O
137
I/O
110
O
71
I/O
28
O
72
I/O
90
O
73
I/O
108
I/O
95
I/O
106
I/O
107
I/O
25
I/O
24
I/O
23
I/O
Description
PC ADDR E S S E NABLE . Active low. When Addres s E nable is
active the 83C795 responds to any host s trobe (IOR , IOW, ME MR ,
ME MW, S ME MR , S ME MW).
PC ADDR E S S LAT CH E NABLE . Us ed to latch valid address es
from the LA bus . Pas s es LA s ignals through internal latches while
high and latches them on falling edge.
BIAS R E S IS T OR . A resistor from BS R to VDD s ets the internal
bias levels . Nominal value is 10KΩ.
PLL F ILT E R CAP. A capacitor (nominal value .01µF) from CAP to
ground is us ed as part of the filter for the internal phas e lock loop.
AUI COLLIS ION. CD+ /CD- are us ed by the external trans ceiver
to s ignal a collis ion by s ending a 10MHz s ignal.
E E R OM Chip S elect. An external 9356 serial E E R OM is used to
store up to 2048 bits of configuration data. T hese s ignals (along
with LLE D and R LE D) interface with that chip.
E E R OM DATA OUT PUT.
GE NE R AL PUR POS E OUT PUT. In s ome sys tems , this bit is wired
to a s hutdown control input of the DC/DC is olated power supply
us ed in 10Bas e2 applications . In other s ys tems , this s upplies a
control s ignal for s witching power s upplies . (T he DC s ignal’s
polarity on the 83C795 is the oppos ite of the 83C790.)
Pers onal Computer BUS CLOCK.
16 BIT I/O S E LE CT E D. Active low. Indicates to the PC/AT bus that
the I/O response will be 16 bits wide. Only us ed for the I/O pipe.
PC I/O R E AD. Active low. R eads an I/O register onto the PC data
bus .
I/O IOR DY. R es pons e to host acces s which can be us ed directly
as ’I/O Channel R eady’ when res ponding to a pers onal computer
bus . It is pulled low (not ready) to lengthen I/O or memory cycles.
When the 83C795 is ready to res pond, the s ignal is driven high
until the host acces s is completed, then becomes tris tated. T his
signal is driven by a tri-s tate buffer capable of s inking 24 mA.
PC I/O WR IT E . Active low. Writes an I/O regis ter from the PC data
bus .
PC INT E R R UPT R E QUE S T LINE S . Active high. T ristated when
not active. IR Q2-9 on the PC/AT bus . IR Q1 is the s ame as the
XT XD pin in s ome test modes .
IR Q3 on PC/AT bus . S ame as XLOOP in s ome test modes .
IR Q5 on PC/AT bus . S ame as XCR S in some tes t modes .
IR Q7 on PC/AT bus . S ame as XR XC in some tes t modes .
IR Q10 on PC/AT bus . S ame as XR XD in s ome tes t modes .
IR Q11 on PC/AT bus . S ame as XCOL in s ome tes t modes.
IR Q15 on PC/AT bus . S ame as XT XC in s ome tes t modes.
TABLE 4-1. 83C795 PIN ASSIGNMENTS
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