83C795 Datasheet, PDF (78/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

LAN CONTROLLER OVERVIEW
83C795
7.0 LAN CONTROLLER OVERVIEW
T he LAN Controller cons is ts of 3 bas ic blocks :
DMA controller, transmitter, and receiver. E ach of
thes e blocks cons is ts of s ub-s ections . T he DMA
controller includes a memory interface unit, control
regis ters , and a micro-coded s equencer that
handles data buffering for the trans mitter and
receiver s ections.
T he trans mitter block has a MAC (Media Access
Control) s ection that performs the IE E E 802.3
trans mis s ion protocol and a P hys ical L ayer
Interface (P L I) s ection that does Manches ter
encoding and drives the cables.
T hereceiver block has aMACs ection that performs
the 802.3 reception protocol and a PLI s ection that
converts line level differential signals to internal
logic s ignals while doing clock recovery, and
manches ter decoding.
7.1 DMA CONTROLLER
T he DMA controller handles data movement
between the F I F Os and buffer memory for
trans miss ion andreception of frames . All DMAdata
traffic is 8-bit wide. One DMA controller is s hared
between the trans mit and receive functions . T he
controller groups memory trans fers into burs ts of 8
bytes for both transmit and receive functions . T he
DMA controller always access es memory by doing
two s ingle-byte trans fers in a row. T he burst size
and its trigger levels are s hown in Table 7-1.
BURST
TRIGGER LEVEL
RX
TX
8 bytes
R ≥8
T ≤8
TABLE 7-1. DMA BURST LENGTH FIELD
T hough internally 8 bits wide, the DMA controller
generates 16-bit addres s es . It acces ses memory in
2 cycles of the chip’s mas ter clock (per byte).
When conducting a loop-back tes t, this controller
can handlefull-duplex bufferingof full length frames
at serial datarates upto10 Mbps . It does nothandle
the general cas e of independent (concurrent)
trans mit and reception proces ses .
7.1.1 Assembly and Disassembly Latches
T hes e latches are us ed to match up the internal
8-bit datapath with theexternal databus . As sembly
latches build a 16-bit word out of two 8-bit words or
s upplies the consecutive bytes when interfacing to
an 8-bit bus . Dis as s embly latches perform the
invers e function. T hes e are us ed during DMA
operations and are bypas s ed when the chip’s
regis ters are written or read.
7.1.2 Memory Interface Unit
T he memory interface unit (MIU) transfers data
from buffer memory to the internal dis as sembly
latches and from the internal ass embly latches to
buffer memory. It is a part of the DMA controller.
T his block generates the memory s tr obes
(R AMOE , R AMWR ) when the DMA is acces sing
the buffer R AM.
MIU operation is initiated by the DMA controller
after it sets upthe address for the trans fer and puts
outgoing data (receiver functions ) into the
as s embly latches . T he MIU then performs the
memory trans fer in the next time s lot as s igned to
the DMA.
T he bas ic DMA cycles are in F igure 7-1. R eal
details can be found in the AC timing s ection.
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