83C795 Datasheet, PDF (63/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
HOST INTERFACE SECTION
6.3.2 I/O Address Decode
T he I/O addres s decoder compares the sys tem
address lines S A15-S A13 and S A8-S A5 against a
programmable value. S A9 is compared to ’1’. T he
lower groupof lines gives awindowsize of 32 bytes
located on 32-byte boundaries over the range of
200H to3E 0H. T hecomparis on with upper address
bits allows the window to be located outs ide the
base I/O area in the event there are multiple LAN
cards on the s ame backplane. T his comparis on is
qualified by the IOR , IOW, and the invers e of the
AE N lines . I/O bas e location pos sibilities are:
0200, 0220, 0240, ..., 03E0
2200, 2220, 2240, ..., 23E0
4200, 4220, 4240, ..., 43E0
...
E200, E220, E240, ..., E3E0
Note
Only the first base location option is
supported by Plug and Play.
T he I/O addres s is further decoded to res olve
between the L AN controller and regis ters
as sociated with the hos t interface bas ed on the A4
address line.
6.3.2.1 PC-98 Bus Support
T his feature allows the I/O addres s decoding to be
changed to s upport the NE C PC-98 bus. T his is
done by installing JUMPE R 7, which connects an
external res is tor between MA7 and ground. When
enabled, the S A9-S A1 lines replace the S A8-S A0
lines , the S A12-S A10 lines mus t be all 1’s , and the
S A0 line mus t be zero for an I/O access to occur.
T his remapping only affects I/O acces s es and
leaves memory decoding unchanged.
6.4 BUS CONTROL SIGNALS
T wo s ignals control much of the bus activity. T hey
are I/O Channel R eady (IOR DY) and Z ero Wait
S tate (Z WS ). E ach is explained below.
6.4.1 IORDY
T he IOR DY output is a high current, tri-s tate driver
which is normally turned off between acces s es to
the board. It will actively drive low to indicate that
the board is not IOR DY and drives high when
making the trans ition from ’not ready’ to ’ready’.
Acces s to the internal regis ters of the L AN
controller is arbitrated by the LAN controller. T his
arbitration is transparent to the hos t.
When host acces s is completed, IOR DY is tri-stated
by the ending of the hos t’s s trobes .
6.4.2 Zero Wait State Response To Host
T he Z ero Wait S tate (Z WS ) s ignal tells the
microproces s or that it can complete the present
bus cycle without ins erting any additional wait
cycles . T he res pons e algorithm for the Z WS line
depends on the memory width, the host access
type, and whether the board has been enabled to
act as a16-bit device. T heappropriate type of Z WS
res pons e logic is s elected on the bas is of memory
width and the M16E N control bit state.
T here is a Z ero Wait E nable bit in one of the hos t
interfaceregis ters (CR .Z WS E N) which can beus ed
to prevent the 83C795 fromas s ertingtheZ ero Wait
S tate s ignal.
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