83C795 Datasheet, PDF (47/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
ETHERNET SYSTEM CONTROLLER REGISTERS
5.2.29 RSTOP - Receive Stop Page Register
Normal Map R ead Port = 2:12
Normal Map Write Port = 0:12
T he R eceive S top Page R egis ter points to the firs t
address beyond the las t receive buffer in the ring
beforewrappingaroundtotheR S TART buffer. Only
A08-A15 are specified s ince all buffers are aligned
on 256-byte boundaries .
BIT
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A09
0 A08
RSTOP
RESET
X
X
X
X
X
X
X
X
5.2.30 RTABH - Receive Buffer Table Pointer
High Register
Linked-List Map R ead/Write Port = 0:19
T his regis ter contains the upper 8 bits for the
regis ter pair us ed as a pointer to the receive buffer
des criptors table. T hes e regis ters s hould be
initializedtothes amevalueas theR BE GIN regis ter
when the descriptor table is created and thereafter
left unaltered unles s the receiver buffer pool is
rebuilt. F or more information, refer to page 89.
BIT
7 A15
6 A14
5 A13
4 A12
3 A11
2 A10
1 A09
0 A08
RTABH
RESET
X
X
X
X
X
X
X
X
5.2.31 RTABL - Receive Buffer Table Pointer
Low Register
Linked-List Map R ead/Write Port = 0:18
T his regis ter contains the lower 8 bits for the
regis ter pair us ed as a pointer to the receive buffer
des criptors table. T hes e regis ters s hould be
initializedtothes amevalueas theR BE GIN regis ter
when the descriptor table is created and thereafter
left unaltered unles s the receiver buffer pool is
rebuilt. F or more information, refer to page 89.
BIT
7 A07
6 A06
5 A05
4 A04
3 A03
2 A02
1 A01
0 A00
RTABL
RESET
X
X
X
X
X
X
X
X
5.2.32 STA0-STA5 - Station Address
Registers
STA
Register
STA0
STA1
STA2
STA3
STA4
STA5
Normal Map
Port Address
Read Write
1:11 1:11
1:12 1:12
1:13 1:13
1:14 1:14
1:15 1:15
1:16 1:16
Linked-List Map
Port Address
Read Write
1:11 1:11
1:12 1:12
1:13 1:13
1:14 1:14
1:15 1:15
1:16 1:16
T hes e 6 regis ters holdthe node’s individual s tation
address . Table5-11 s hows thebits definedfor these
regis ters.
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