83C795 Datasheet, PDF (57/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
HOST INTERFACE SECTION
6.0 HOST INTERFACE SECTION
T he Hos t Interface is a configurable interface
between an Indus try S tandard Architecture bus
(like IBM PC/XT /AT ) and the LAN controller with its
buffer memory. T he interface is a s lave peripheral
with s haredR AM ands upport for an Initial Program
Load R OM.
T hebas icfunctions of thehos t interfacesection are
the:
• Address decode
• Memory address generation
• Retrieval and storage of configuration parame-
ters and LAN address
• Interrupt mapping and control
• Control over certain HW functions for support
circuitry
6.1 MEMORY CACHE
T he memory cache in the 83C795 cons is ts of a
4-byte-deepF IF O which s erves as an intermediate
buffer between the IS A bus and the local buffer
R AM. F or read operations , the cache acts as a
s mall prefetch buffer which fills itself with datafrom
locations in the buffer R AM that depend on the
address of the las t data location read by the hos t.
F or write operations , the cache acts as several
temporary regis ters that can be as ynchronous ly
written by the host, then s ynchronously flus hed to
buffer R AM as time permits . T his method provides
s everal advantages over previous methods :
• Host accesses to shared memory can be
treated more like register accesses, thus simpli-
fying zero-wait state timing.
• A single 8-bit wide buffer RAM is used but the
chip can accommodate 8- or 16-bit accesses by
the host.
• Asynchronous arbitration between the host and
the DMA controller for access to the buffer RAM
is not necessary.
In addition to thedataF IF O, the cacherequires two
address counters for its operation. T he firs t, called
the Host Counter, is compared with the incoming
hos t addres s . T he s econd, called the B uffer
Counter, is usedtogeneratetheaddres s tothelocal
buffer R AM. T he s ame data F IF O is us ed for both
reads andwrites res ultingin two different modes of
operation: R ead Mode and Write Mode.
R E AD MODE
If the hos t address does not equal the value in the
Hos t Counter, then both counters are loaded with
the incoming addres s . T hen the cache is filled with
data from the buffer R AM a byte at a time by
incrementing the Buffer Counter. T he hos t access
is s talled during this time by driving the IOR DY
s ignal low. Once the cache has avalidwordof data
fromthe buffer R AM, the IOR DY line is driven high.
T his s ignals the host that the data is valid, and the
host, in turn, ends the access . Once the hos t has
finis hed, the Hos t Counter is incremented (the
increment s tep will be either 1 or 2 depending on
whether the hos t access was for a byte or for a
word), and the F IF O pointers are updated. T he
cache continues to fill with data as long as there is
room in the F IF O. If the hos t addres s matches the
value in the Hos t Counter (andthere is validdatain
the cache), the read can be s erviced immediately.
WR IT E MODE
T he Write Mode is handled like the R ead Mode
except that thedatamoves in theoppos itedirection
through the F IF O. Als o, if an addres s mis s occurs
in write mode, the cache mus t firs t flush all valid
data in the F IF O out to the buffer R AM before
loading new values into the addres s counters.
T he IOR DY signal is us ed when the cache needs
to s tall a hos t access . T his s ignal is outputted by a
high current, tri-s tatable driver which is normally
turned off between acces s es to the board. It drives
low to indicate that the board is not IOR DY and
drives high when making the trans ition from ’not
ready’ to ’ready’.
When the acces s completes , the IOR DY line is
tri-statedby the endingof thehost’s s trobes . F igure
6-1 depicts the memory cache arrangement.
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