83C795 Datasheet, PDF (85/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

83C795
LAN CONTROLLER OVERVIEW
7.4.7.1 Early Receive Failure Detection
During the reception of a frame with early receive
enabled, it is pos s iblefor thehos t toreadframedata
from the buffer R AM before the DMA writes it if the
early receive thres hold is set too low. T he failure
detection logicenables the hos t to detect if this has
happened; if s o, it goes back and recopies the
correct data.
T helogicrequiredfor this is similar tothelogicus ed
for early transmit underrun detection. T he local
memory addres s is latched every time the DMA
writes to the buffer R AM. When the memory cache
or I/O pipe reads data from the R AM, the local
memory addres s is compared to the las t latched
addres s . (T he leas t s ignificant 2 bits are not
compared s o the detection mechanis m has a
granularity of 4 bytes ). T his comparison is turned
off when the DMA finishes placing the frame in
s hared memory. If the two address es are equal,
E R F BIT (UBR CV.1) is s et and the latched address
is s tored in the E R FA regis ters (E R FAL and
E R FAH). When the host reads that E R F BIT is s et,
it should begin recopying data from a point at or
before E R FA and res et E R F BIT.
Note
The value in ERFA contains the local
memory address where the failure oc-
curred, not the host address.
T he E R FA regis ters remain s et until the host clears
theE R F BIT. F or moreon E R F BIT, s eepage40. F or
more on the E R FA registers , s ee page 22.
7.4.8 Receive Protocol FSM
T he R eceive Protocol F S M controls reception of
frames, checks for errors , and posts s tatus to a
regis ter after completion of each reception. It
operates counters for the number of bytes in the
frame and for three types of error conditions . T he
receiver protocol F S M can be configured via a
regis ter, allowingsomeflexibility as towhich frames
are to be received.
T hereceivedbytecounter is 16-bits wide. T hethree
error counters are each 8-bits wide. T hes e will
count fromzeroupto255, where they s tick toavoid
wrap-around. T he error counters are s elf-clearing
when readandthey can generateasharedinterrupt
condition when any of themhavecountedupto192.
T heR eceiveProtocol F S Minterfaces with theDMA
s ection to coordinate buffering of received frames .
It informs the DMA of abort conditions, s hould they
occur as well as valid completions of received
frames . After the frame has been buffered to
memory by the DMA, the DMA s ection copies the
R eceiver S tatus R egis ter (R S T AT ) and the number
of bytes received from the receiver into the header
of the buffer.
T he receiver F IF O is monitored for overflow
conditions and if one occurs, frame reception is
terminated and an error flag is pos ted to the S tatus
R egis ter.
T heR eceiver s ection is enabledby s ettingtheS tart
andclearingtheS topbits in theCommandR egis ter
- CMD.S T A and CMD.S T P. Until enabled, the
receiver s ection ignores incomingframes . Oncethe
S tart bit has been s et, it remains true internally until
the S top bit is set or the chip is res et. Clearing the
S tart bit in Command R egis ter does not caus e the
receiver s ection to s top operating.
If the S top bit is s et while receiver is operational, it
will completethehandlingof any ongoingframeand
then go to a s oft res et condition, ignoring new
incomingframes . T hereceiver will clear theR S T AT
R egis ter when the current frame is finis hed and
pos ted. When both trans mitter and receiver
s ections are s topped, the R S T bit in the interrupt
s tatus regis ter will bes et. It s houldbenotedthat the
DMAcontroller may remain activewhile S topis s et.
T he protocol machine can beconfiguredto operate
in a "Monitor Mode" which checks validity of
incoming frames and maintains error s tatis tics for
thembut does not storethemin memory. E ach time
an acceptable frame is completed while in this
mode, the Mis s ed Packet Counter (MPCNT ) is
incremented. T his counter is not incremented by
F IF O overflows .
7.4.9 Reception Process
IE E E 802.3 packets consist of thes e fields and are
therefore proces s ed in this order:
• Preamble field
• SFD field
• DA field
• SA field
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