83C795 Datasheet, PDF(50/136 Page) List of Unclassifed Manufacturers

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83C795 Datasheet, PDF (50/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

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ETHERNET SYSTEM CONTROLLER REGISTERS

83C795

LB1 LB0

Operation

0 0 Normal (no loopback)

0 1 Internal loopback (before MAN

CODEC)

1 0 Internal loopback, LOOP pin is high

(after MAN CODEC)

1 1 External loopback with LOOP pin low

TABLE 5-12. LOOPBACK TEST SELECTION

Bit 0: CRCN, CRC Generation Inhibition

S etting this bit inhibits generation of CR C during

trans miss ion of frame. T he us er is res pons ible for

calculating the frameâs CR C and placing it in the

buffer in s uch a way that when the las t 4 bytes of

thebuffer ares hiftedout, they formthecorrect CR C

for the frame. Note that the s erializer s hifts bytes

outLS B first whereas theCR Cmust bes hiftedMS B

firs t. T he operation of the receiver is not affectedby

this bit.

5.2.39 TDOWNH - Transfer Count High

Linked-List Map R ead/Write Port = 2:1B

T his regis ter contains the upper 8 bits for the

regis ter pair us ed by the DMA controller as a

s cratch pad for the bytes remaining to trans fer

count during the transmis sion proces s . T hey can

be acces sed for manufacturing test purpos es .

Note

Writing to these registers while commu-

nication is taking place may cause er-

rors in the DMA process.

BIT

7 A15

6 A14

5 A13

4 A12

3 A11

2 A10

1 A09

0 A08

TDOWNH

RESET

5.2.40 TDOWNL - Transfer Count Low

Linked-List Map R ead/Write Port = 2:1A

T his regis ter contains the lower 8 bits for the

regis ter pair us ed by the DMA controller as a

s cratch pad for the bytes remaining to trans fer

count during the transmis sion proces s . T hey can

be acces sed for manufacturing test purpos es .

Note

Writing to these registers while commu-

nication is taking place may cause er-

rors in the DMA process.

BIT

7 A07

6 A06

5 A05

4 A04

3 A03

2 A02

1 A01

0 A00

TDOWNL

RESET

5.2.41 TEND - Transfer Buffer End Register

Linked-List Map R ead Port = 2:14

Linked-List Map Write Port = 0:14

T his regis ter holds the upper 8 bits of the firs t

addres s beyond the end of the trans mit buffer

descriptor table. T he lower 8 bits are as s umed to

be zero. T he table lies between (T BE GIN * 256)

and (T E ND * 256 - 1). R efer to page 80 for more

information.

BIT

7 TE15

6 TE14

5 TE13

4 TE12

3 TE11

2 TE10

1 TE9

0 TE8

TEND

RESET

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