83C795 Datasheet, PDF (42/136 Pages) List of Unclassifed Manufacturers – Ethernet System Controller

ETHERNET SYSTEM CONTROLLER REGISTERS
83C795
5.2.15 MANCH - Manchester Management
Register
Normal Map R ead/Write Port = 3:1F
Linked-List Map R ead/Write Port = 3:1F
T his regis ter allows the reading back of the
10Bas eT s tatus LE D drivers tosupport network and
s tation management functions . It als o enables and
contr ols the 83C795’s internal Manches ter
encoder/decoder.
Bit 2: LLED, Link Status LED Readback
When LLE D = 1, this LE D is on (output s inking
current).
Bit 1: RLED, Receive LED Readback
When R LE D = 1, this LE D is on (output s inking
current).
Bit 0: TLED, Transmit LED Readback
When T LE D = 1, this LE D is on (output s inking
current).
BIT
MANCH
7 MANDIS
6 SEL
50
4 ENAPOL
3 PLED
2 LLED
1 RLED
0 TLED
RESET
0
1
0
1
0
0
0
0
Bit 7: MANDIS, Manchester Disable
MANDIS = 1 - dis ables the internal Manches ter
E ncoder/Decoder. When dis abled, the LAN Con-
troller us es the decoder s erial interface cons is ting
of thes e lines : XT XD, XT XE , XT XC, XR XD, XR XC,
XCR S , XCOL, XLOOP.
MANDI S = 0 - E nabl es the Manches ter
E ncoder/Decoder.
Bit 6: SEL, Select AUI Mode For Idle State
S E L = 0 - T X+ is pos itive in relation to T X-.
S EL = 1 - T X+ = T X-.
Bit 4: ENAPOL, Automatic Polarity Correct
E NAPOL = 1 - E nable Auto Polarity Correct
E NAPOL = 0 - Dis able Auto Polarity Correct
Bit 3: PLED, TPRX Polarity LED Readback
When PLE D = 1, this LE D is on.
Note
There is no P L E Dpin onto which this
signal might be driven.
5.2.16 MPCNT - Missed Packet Error Counter
Register
Normal Map R ead Port = 0:1F Linked-List Map
R ead Port = 0:1F
T his regis ter is incremented by the receive unit
whenever it cannot receive a packet due to a lack
of receive buffers , receive F IF O overflow, or
becaus e the receiver is in monitor mode. Only
packets whos e addres s is recognized will be
included in this tally. T he counter will increment to
255 and stick if additional packets are mis s ed. T he
counter is cleared when read.
BIT
7 CT7
6 CT6
5 CT5
4 CT4
3 CT3
2 CT2
1 CT1
0 CT0
MPCNT
RESET
0
0
0
0
0
0
0
0
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