SAM4L_14 Datasheet, PDF (79/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
8.9.6
8.9.7
8.9.8
Security Considerations
In protected state this module may access sensible information located in the device memories.
To avoid any risk of sensible data extraction from the module registers, all operations are non
interruptible except by a disable command triggered by writing a one to CR.DIS. Issuing this
command clears all the interface and internal registers.
Some registers have some special protection:
• It is not possible to read or write the LENGTH register when the part is protected.
• In addition, when the part is protected and an operation is ongoing, it is not possible to read
the ADDR and DATA registers. Once an operation has started, the user has to wait until it has
terminated by polling the DONE field in the Status Register (SR.DONE).
Chip Erase
The Chip erase operation consists in:
1. clearing all the volatile memories in the system
2. clearing the whole flash array
3. clearing the protected state
No proprietary or sensitive information is left in volatile memories once the protected state is
disabled.
This feature is operated by writing a one to the CE bit of the Control Register (CR.CE). When the
operation completes, SR.DONE is asserted.
Cortex-M4 Core Reset Source
The SMAP processes the EDP Core hold reset requests (Refer to Section 1.1.8 ”SMAP Core
Reset Request Source” on page 6). When requested, it instructs the Power Manager to hold the
Cortex-M4 core under reset.
The SMAP can de-assert the core reset request if a one is written to the Hold Core Reset bit in
the Status Clear Register (SCR.HCR). This has the effect of releasing the CPU from its reset
state. To assert again this signal, a new reset sequence with TCK tied low must be issued.
Note that clearing HCR with this module is only possible when it is enabled, for more information
refer to Section 8.9.4 ”Initializing the Module” on page 78. Also note that asserting RESET_N
automatically clears HCR.
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