SAM4L_14 Datasheet, PDF(170/176 Page) ATMEL Corporation – Technology for Ultra-low Power Consumption

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SAM4L_14 Datasheet, PDF (170/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

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12.1.5 TC

12.1.6 USBC

ATSAM4L8/L4/L2

Fix/Workaround

Read the last received data, then perform a software reset by writing a one to the Software

Reset bit in the Control Register (CR.SWRST).

Disabling SPI has no effect on the SR.TDRE bit

Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered

when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is

disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer

is empty, and this data will be lost.

Fix/Workaround

Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the

SPI and PDCA.

SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and

NCPHA=0

When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one

(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,

then an additional pulse will be generated on SCK.

Fix/Workaround

When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1

if CSRn.CPOL=1 and CSRn.NCPHA=0.

Channel chaining skips first pulse for upper channel

When chaining two channels using the Block Mode Register, the first pulse of the clock

between the channels is skipped.

Fix/Workaround

Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle

for the upper channel. After the dummy cycle has been generated, indicated by the

SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real

values.

In USB host mode, entering suspend mode for low speed device can fail when the

USB freeze (USBCON.FRZCLK=1) is done just after UHCON.SOFE=0.

Fix/Workaround

When entering suspend mode (UHCON.SOFE is cleared), check that USBFSM.DRDSTATE

is not equal to three before freezing the clock (USBCON.FRZCLK=1).

In USB host mode, the asynchronous attach detection (UDINT.HWUPI) can fail when

the USB clock freeze (USBCON.FRZCLK=1) is done just after setting the USB-

STA.VBUSRQ bit.

Fix/Workaround

After setting USBSTA.VBUSRQ bit, wait until the USBFSM register value is

âA_WAIT_BCONâ before setting the USBCON.FRZCLK bit.

42023GSâSAMâ03/2014

170

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