SAM4L_14 Datasheet, PDF (42/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
4.8 Peripheral Debug
The PDBG register controls the behavior of asynchronous peripherals when the device is in
debug mode.When the corresponding bit is set, that peripheral will be in a frozenstate in debug
mode.
4.8.1 Peripheral Debug
Name:
PDBG
Access Type:
Read/Write
Address:
0xE0042000
Reset Value:
0x00000000
31
30
29
28
27
26
25
-
-
-
-
-
-
-
23
22
21
20
19
18
17
-
-
-
-
-
-
-
15
14
13
12
11
10
9
-
-
-
-
-
-
-
7
6
5
4
3
2
1
-
-
-
-
-
PEVC
AST
• WDT: Watchdog PDBG bit
WDT = 0: The WDT counter is not frozen during debug operation.
WDT = 1: The WDT counter is frozen during debug operation when Core is halted
• AST: Asynchronous Timer PDBG bit
AST = 0: The AST prescaler and counter is not frozen during debug operation.
AST = 1: The AST prescaler and counter is frozen during debug operation when Core is halted.
• PEVC: PEVC PDBG bit
PEVC= 0: PEVC is not frozen during debug operation.
PEVC= 1: PEVC is frozen during debug operation when Core is halted.
24
-
16
-
8
-
0
WDT
42
42023GS–SAM–03/2014