SAM4L_14 Datasheet, PDF (152/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
Table 9-66. SWD Timings⁽¹⁾
Symbol
Parameter
Conditions
Min
Thigh
Tlow
Tos
Tis
Tih
SWDCLK High period
10
SWDCLK Low period
V_VDDIO from
10
3.0V to 3.6V,
SWDIO output skew to falling edge SWDCLK
maximum
-5
Input Setup time required between SWDIO
external
capacitor =
4
Input Hold time required between SWDIO and
rising edge SWDCLK
40 pF
1
Max
500 000
500 000
5
-
-
Units
ns
Note: 1. These values are based on simulation. These values are not covered by test limits in production or characterization.
42023GS–SAM–03/2014
152