SAM4L_14 Datasheet, PDF (39/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
4.6 Cortex-M4 implementations options
This table provides the specific configuration options implemented in the SAM4L series
Option
Implementation
Inclusion of MPU
yes
Inclusion of FPU
No
Number of interrupts
80
Number of priority bits
4
Inclusion of the WIC
No
Embedded Trace Macrocell No
Sleep mode instruction
Only WFI supported
Endianness
Little Endian
Bit-banding
No
SysTick timer
Yes
Register reset values
No
Table 4-1. Cortex-M4 implementation options
4.7 Cortex-M4 Interrupts map
The table below shows how the interrupt request signals are connected to the NVIC.
Table 4-2.
Line
0
1
2
3
4
5
6
7
8
9
10
11
Interrupt Request Signal Map (Sheet 1 of 3)
Module
Flash Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Signal
HFLASHC
PDCA 0
PDCA 1
PDCA 2
PDCA 3
PDCA 4
PDCA 5
PDCA 6
PDCA 7
PDCA 8
PDCA 9
PDCA 10
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42023GS–SAM–03/2014