SAM4L_14 Datasheet, PDF (53/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
6.2.4 Power-up Sequence
6.2.4.1
Maximum Rise Rate
To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values
described in Table 9-3 on page 100.
6.2.4.2
Minimum Rise Rate
The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply
requires a minimum rise rate for the VDDIN power supply.
See Table 9-3 on page 100 for the minimum rise rate value.
If the application can not ensure that the minimum rise rate condition for the VDDIN power sup-
ply is met, the following configuration can be used:
• A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.6 V.
6.3 Startup Considerations
This section summarizes the boot sequence of the ATSAM4L8/L4/L2. The behavior after power-
up is controlled by the Power Manager. For specific details, refer to Section 9. ”Power Manager
(PM)” on page 677.
6.3.1
Starting of Clocks
After power-up, the device will be held in a reset state by the power-up circuitry for a short time
to allow the power to stabilize throughout the device. After reset, the device will use the System
RC Oscillator (RCSYS) as clock source. Refer to Section 9. ”Electrical Characteristics” on page
99 for the frequency for this oscillator.
On system start-up, the DFLL and the PLLs are disabled. Only the necessary clocks are active
allowing software execution. Refer to Section 3-6 ”Maskable Module Clocks in AT32UC3B.” on
page 24 to know the list of peripheral clock running.. No clocks have a divided frequency; all
parts of the system receive a clock with the same frequency as the System RC Oscillator.
6.3.2
Fetching of Initial Instructions
After reset has been released, the Cortex M4 CPU starts fetching PC and SP values from the
reset address, which is 0x00000000. Refer to the ARM Architecture Reference Manual for more
information on CPU startup. This address points to the first address in the internal Flash.
The code read from the internal flash is free to configure the clock system and clock sources.
6.4 Power-on-Reset, Brownout and Supply Monitor
The SAM4L embeds four features to monitor, warm, and/or reset the device:
• POR33: Power-on-Reset on VDDANA
• BOD33: Brownout detector on VDDANA
• POR18: Power-on-Reset on VDDCORE
• BOD18: Brownout detector on VDDCORE
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