SAM4L_14 Datasheet, PDF (69/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
8.7.5 Product Dependencies
8.7.5.1
I/O Lines
The TCK pin is dedicated to the EDP. The other debug port pins default after reset to their GPIO
functionality and are automatically reassigned to the JTAG functionalities on detection of a
debugger. In serial wire mode, TDI and TDO can be used as GPIO functions. Note that in serial
wire mode TDO can be used as a single pin trace output.
8.7.5.2
Power Management
When a debugger is present, the connection is kept alive allowing debug operations. As a side
effect, the power is never turned off. The hot plugging functionality is always available except
when the system is in BACKUP Power Save Mode.
8.7.5.3
Clocks
The SWJ-DP uses the external TCK pin as its clock source. This clock must be provided by the
external JTAG master device.
Some of the JTAG Instructions are used to access an Access Port (SMAP or AHB-AP). These
instructions require the CPU clock to be running.
If the CPU clock is not present because the CPU is in a Power Save Mode where this clock is
not provided, the Power Manager(PM) will automatically restore the CPU clock on detection of a
debug access.
The RCSYS clock is used as CPU clock when the external reset is applied to ensure correct
Access Port operations.
8.7.6
Module Initialization
This module is enabled as soon as a TCK falling edge is detected when RESET_N is not
asserted (refer to Section 8.7.7 below). Moreover, the module is synchronously reseted as long
as the TAP machine is in the TEST_LOGIC_RESET (TLR) state. It is advised asserting TMS at
least 5 TCK clock periods after the debugger has been detected to ensure the module is in the
TLR state prior to any operation. This module also has the ability to maintain the Cortex-M4
under reset (refer to the Section 8.7.8 ”SMAP Core Reset Request Source” on page 70).
8.7.7
Debugger Hot Plugging
The TCK pin is dedicated to the EDP. After reset has been released, the EDP detects that a
debugger has been attached when a TCK falling edge arises.
Figure 8-4. Debugger Hot Plugging Detection Timings Diagram
TCK
TCK
RESET_^RN^{E S E T _ N}
Hot_^Hp^ol^tu^Pg^lug^gi^gnⁱⁿg^g
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42023GS–SAM–03/2014