SAM4L_14 Datasheet, PDF (37/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
sor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically
reducing the interrupt latency. This is achieved through the hardware stacking of registers, and
the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not
require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain
optimization also significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep
sleep function enabling the entire device to be rapidly powered down while still retaining pro-
gram state.
4.2 System level interface
The Cortex-M4 processor provides multiple interfaces using AMBA^® technology to provide high
speed, low latency memory accesses. It supports unaligned data accesses and implements
atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe
Boolean data handling.
The Cortex-M4 processor has an memory protection unit (MPU) that provides fine grain memory
control, enabling applications to utilize multiple privilege levels, separating and protecting code,
data and stack on a task-by-task basis. Such requirements are becoming critical in many
embedded applications such as automotive.
4.3 Integrated configurable debug
The Cortex-M4 processor implements a complete hardware debug solution. This provides high
system visibility of the processor and memory through either a traditional JTAG port or a 2-pin
Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside
data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system
events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated
messages, data trace, and profiling information through a single pin.
The Flash Patch and Breakpoint Unit (FPB) provides 8 hardware breakpoint comparators that
debuggers can use. The comparators in the FPB also provide remap functions of up to 8 words
in the program code in the CODE memory region. This enables applications stored on a non-
erasable, ROM-based microcontroller to be patched if a small programmable memory, for exam-
ple flash, is available in the device. During initialization, the application in ROM detects, from the
programmable memory, whether a patch is required. If a patch is required, the application pro-
grams the FPB to remap a number of addresses. When those addresses are accessed, the
accesses are redirected to a remap table specified in the FPB configuration, which means the
program in the non-modifiable ROM can be patched.
A specific Peripheral Debug (PDBG) register is implemented in the Private Peripheral Bus
address map. This register allows the user to configure the behavior of some modules in debug
mode.
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