SAM4L_14 Datasheet, PDF (67/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
8.7 Enhanced Debug Port (EDP)
Rev.: 1.0.0.0
8.7.1 Features
• IEEE1149.1 compliant JTAG debug port
• Serial Wire Debug Port
• Boundary-Scan chain on all digital pins for board-level testing
• Debugger Hot-Plugging
• SMAP core reset request source
8.7.2
Overview
The enhanced debug port embeds a standard ARM debug port plus some specific hardware
intended for testability and activation of the debug port features. All the information related to the
ARM Debug Interface implementation can be found in the ARM Debug Interface v5.1 Architec-
ture Specification document.
It features:
• A single Debug Port (SWJ-DP), that provides the external physical connection to the interface
and supports two DP implementations:
– the JTAG Debug Port (JTAG-DP)
– the Serial Wire Debug Port (SW-DP)
• A supplementary JTAG TAP (BSCAN-TAP) connected in parallel with the JTAG-DP that
implements the boundary scan instructions detailed in
• A JTAG-FILTER module that monitors TCK and RESET_N pins to handle specific features
like the detection of a debugger hot-plugging and the request of reset of the Cortex-M4 at
startup.
The JTAG-FILTER module detects the presence of a debugger. When present, JTAG pins are
automatically assigned to the Enhanced Debug Port(EDP). If the SWJ-DP is switched to the SW
mode, then TDI and TDO alternate functions are released. The JTAG-FILTER also implements a
CPU halt mechanism. When triggered, the Cortex-M4 is maintained under reset after the exter-
nal reset is released to prevent any system corruption during later programmation operations.
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