SAM4L_14 Datasheet, PDF (151/176 Pages) ATMEL Corporation – Technology for Ultra-low Power Consumption

ATSAM4L8/L4/L2
Table 9-65.
Symbol
JTAG0
JTAG1
JTAG2
JTAG3
JTAG4
JTAG5
JTAG6
JTAG7
JTAG8
JTAG9
JTAG10
JTAG Timings⁽¹⁾
Parameter
TCK Low Half-period
TCK High Half-period
TCK Period
TDI, TMS Setup before TCK High
TDI, TMS Hold after TCK High
TDO Hold Time
TCK Low to TDO Valid
Boundary Scan Inputs Setup Time
Boundary Scan Inputs Hold Time
Boundary Scan Outputs Hold Time
TCK to Boundary Scan Outputs Valid
Conditions
Min
21.8
8.6
30.3
2.0
V_VDDIO from
3.0V to 3.6V,
2.3
maximum
external
9.5
capacitor =
40 pF
0.6
6.9
9.3
Max
21.8
32.2
Note: 1. These values are based on simulation. These values are not covered by test limits in production.
9.10.6 SWD Timing
Figure 9-18. SWD Interface Signals
Read Cycle
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Stop
Park
Tos
Tri State
Thigh
Tlow
Tri State
Acknowledge
Data
Data
Tri State
Write Cycle
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Stop
Park
Tri State
Tri State
Tis
Tih
Acknowledge
Data
Data
Parity
Units
ns
Parity
Start
Start
Tri State
42023GS–SAM–03/2014
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